STRONG ARM SA1110 USB Solution

xiaoxiao2021-03-06  118

STRONG ARM SA1110 USB Solution

USB Interface Solution for Strong ARM SA1110

■ Luoyang Industrial College Computer Department Li Meng Shu Yunxing

Since Intel Strong ARM SA1110 is up to 206MHz's frequency speed, and has a powerful multimedia interface and LCD interface, a wide range of applications in handheld and some industry users, such as telecommunications multimedia publication and VoIP mobile terminals, etc. . However, since the SA1110's USB interface can only be used from the controller, it can only be used as a slave device, limiting the application range of SA1110, so how to expand the USB of the USB will become a key problem. This uses Philips's ISP1161 to extend the two USB primary interfaces and a slave interface for SA1110. ISP1161 Function Introduction ISP1161 is integrated with two USB controllers on one chip, one is the host controller HC (Host Controller), the other is from the controller DC (Device Controller), the two controller shared bus interface, There is a separate DMA channel and a separate DMA interrupt application pin, standalone primary interface, and slave interface, so ISP1161 controls the USB HC and DC work. The ISP1161 provides two downstream ports for USB HC, providing a USB DC with an uplink port. Each downstream port has a separate overcurrent detection input pin and power supply switch control output pin. The uplink interface has a stand-alone VBUS detection input pin, so it can extend the two USB primary interfaces and one slave interface for SA1110. USB's primary interface can be connected to any USB device compatible with USB interface protocol, and USB's slave interface can be connected to a USB interface protocol compatible with a USB primary interface. At the same time, USB HC and DC have independent wakeup input pins and suspend output pins, making system power management more flexible, so ISP1161 is ideal for embedded systems and portable devices. Apply in an embedded system using ISP1161 is shown in Figure 1. The ISP1161 performance indicator ISP1161 supports USB2.0 protocol, and is compatible with USB1.1; supports single-circuit burst mode and DMA operation of multiple burst modes; built-in independent buffer HC (4KB) and DC (2462bit); Voltage 5V or 3.3V; 8kV ESD circuit protection; the maximum transfer of the main interface is 15Mb / s, from the maximum transfer of 11.1Mb / s; 6MHz crystal, internal integration of PLL to reduce electromagnetic interference (EMI). Connection method ISP1161 and CPU interface. It is designed for the CPU designed for RISC, and data transmission can work in I / O port mode and DMA way. There is a "pong" structure of the "Ping Pong" structure can be controlled by the internal master / slave controller or external CPU. The assignment of this RAM space is independent to the main controller and from the controller. The main controller has 2K PING RAM and 2K PONG RAM, from the controller with 1.5K Ping Ram and 1.5K PONG RAM. The D0-D16 of the ISP1161 is connected directly to the data line of SA1110, and the internal registers of ISP 1161 are selected with the two address lines (A0, A1) of SA110. A1A0 = 00 Select the data port of the main controller; A1A0 = 01 Select the command port of the main controller; A1A0 = 10 Select the data port from the controller; A1A0 = 11 Select the command port of the controller. A certain address end, WR, and RD are allocated to ISB1161 with an SA1110, and the WR and RD are transmitted and read respectively. INT1 and INT2 are the main / slave control interrupt applications, and the two interrupt lines can be programmable as levels or pulse triggers. The reset_out / n of the ISP1161, the RESET_OUT / N, RESET_OUT / N will automatically generate a low level to reset the ISP1161 after the SA1110 reset. The connection relationship is shown in Figure 2.

转载请注明原文地址:https://www.9cbs.com/read-100941.html

New Post(0)