TMS320C54X chip introduction
1. Overview
TI is TMS that has been well known
320C
1X, TMS
320C
25, TMS
320C
3x / 4x, TMS
320C
5x, TMS
320C
The 8X basis has developed three new DSP series, which is: TMS
320C
2000, TMS
320C
5000, TMS
320C
The 6000 series has become the mainstream products of Ti DSP during the current and future periods of Ti DSP, and the old model products mentioned earlier will be replaced by these three new series of products.
Features of three new TMS320 DSP series
TTMS
320C
2000 - Best DSP for control, can replace the old 'C1x and' C2X. Now there is a trend in the following two directions:
(1) 'C20x 16-bit DSP, the speed is 20MIPS, the main purpose is the telephone, digital camera, vending machine, etc., where:' F206 has a flash memory.
(2) 'C24x 16-bit DSP, speed is 20MIPS, used as digital motor control, industrial automation, power conversion system, air conditioning, etc.
2.TMS
320C
5000 - low power consumption high performance DSP, 16-bit point, speed 40 ~ 200MIPS. The main purpose is wired and wireless communication, IP, portable information system, pager, hearing aid, and the like.
At present, there are three new members in the 'C5000 series, one is' C5402, this is a cheap DSP, the target price is $ 5 (50K batch), the speed is kept 100MIPS, the in-chip storage space is slightly smaller, RAM is 16K, ROM is 4K. The main application object is wireless MODEM, a new generation of PDAs, network phones and other telephone systems, and consumer electronics.
The second is' C5420, which has two DSP cores, speed reaches 200MIPS, 200K-piece RAM, power consumption 0.32mA / MIPS, 200MIPS does not exceed 120MW, which is the lowest power consumption. The 'C5420 is the most integrated fixed-point DSP, suitable for multi-channel base stations, servers, modems, and telephone systems, etc., require high performance, low power, small size.
The third is' C5416, which is the first model in the 0.15μm device of TI, with three multi-channel buffer serial port (MCBSPS), can be directly coupled to T1 or E1 line, no external logic circuit There are 128K in-chip RAM. Applications are VoIP, communication servers, PBX (special small switches), and computer telephony systems.
3.TMS
320C
6000 - this is TI's high-performance DSP that pushes the market in February 1997, combines all the advantages of the current DSP, with the best cost performance and low power consumption. The 'C6000 series is divided into two types and floating point.
(1) C62xx 16-bit DSP, speed is 1200 ~ 2000MIPS for wireless base station, ADSL MODEM, network system, central bureau switch, digital audio broadcast equipment, etc.
(2) C67xx 32-bit floating point DSP, speed is 1GFLOPS, used for digital beamforming, medical image processing, speech recognition, 3-D graphics, etc.
The new generation of DSPs in TI described above have replaced the old generation of products in the early 1980s and in the early 1990s, and have gained extensive applications in the electronic information industry. The 'C2000 Series has been used for digital motor control, digital camera, PC camera;' C5000 series for honeycomb mobile phones, program-controlled exchange; 'C6000 series for base stations, ADSL, V.90 56K MODEM.
The chip used in this design is a TMS320C with the 'C5000 series.
54x chip. The following focuses on.
2. TMS
320C
54x chip review
2.1 Bus Structure
C54x includes a bus between 8 16-bit widths, where:
l A program bus (PB)
l Three data buses (CB, DB, EB)
l Four address buses (PAB CAB DAB EAB)
2.2 C
P u
C54x's CPU structure includes:
l 40 bits ALU, its input from 16-bit immediate number, 16 bits from data memory data, temporary memory, T, two 16-bit words in data storage, 32-bit words, accumulator 40% in the middle.
l 2 40-bit accumulators, divided into three parts, protected positions (39-32 bits), high words (31-16 bits), low words (15-0 bits).
l Barrel shifter, a left shift of 0 to 31 bits or right movement of 0 to 16 bits.
l 17x17 bits multiplier
l 40 bits adder
l Compare selection and storage unit CSSU
l Data address generator DAGEN
l Program address generator PAGEN
2.3 peripherals
C54x includes
l General I / O pin, XF and BIO
l timer
l PLL clock generator
l HPI port 8 bits or 16 bits
l Synchronous serial port
L with cache serial port BSP
l multi-channel cache serial port MCBSP
l Time division multiplexed serial TDM
l Programmable waiting state generator
l Programmable Bank Switching Module
l external bus interface
l IEEE1149.1 standard JTAG port
3. Memory
In general, the C54X has a storage space of 192k16 to character, 64K program space, 64K data space, 64ki / o space.
Relying on its parallel process characteristics and performance of on-chip RAM two-way access, C54x can perform 4 rows of parallel memory operations: Take instructions, two operands read, one operand write.
There are three advantages in the in-chip memory: high speed (no waiting), low overhead, low power consumption.
3.1 Storage space allocation map (as described in C 5 4 9)
figure 2-
1 '
C54X storage space allocation diagram
After the reset, the interrupt vector table is located in the program area FF80H position, which can be repositioned to any 128-word page of the program space (its address height 9 bit, page number is determined by IPTR in PMST).
3.2 Program Storage Area
C54x has a slice of ROM, DARAM, SARAM, which can be configured to program space through software. When the address is falling in these areas, these areas are automatically accessed, and access to external memory is automatically generated outside of these areas.
3.2 .1
In-chip R o m
In-chip ROM (4K 16K 24K 28K or 48K word) may include:
l Booter, you can boot from serial port, external memory, I / O port or HPI port
L256 word rate expansion table
L256 word A rate expansion table
l 256 words sine table
l interrupt vector table
3.2.2
Expansion program memory
'548,'
549
'
5410, '5420 makes addressable programs
There is 8192k word between 8192k, which is depends on:
l 23 address line
l extended program counter XPC
L6 instructions accessing external program space
When the program space can use the on-chip RAM, each page of the program space is divided into the following two parts: the general block of the maximum 32k word and the proprietary block of 32K words, and the general block is shared all of the page. The XPC register indicates the selected page, after reset, it is initialized to 0, and 6 instructions affecting the XPC are:
l FB [D] Long jump instruction
l FBACC [D] Long jump instruction, the jump address is determined by the contents of A or B
l Fcala [D] Long-modified instruction, the subroutine address is determined by the contents of A or B
l fcall [d] long call command
l Fret [D] Long Return Instruction
l Frete [D] Long Interrupt Returns
Other instructions do not modify the XPC register and do internal access in the current page.
3.3 Memory Image Register (Take 5 4 9 as an Example)
0
IMR
Interrupt shield register
1
IFR
Interrupt flag register
2 - 5
-
Test
6
ST0
Status register 0
Seduce
ST1
Status register 1
8
Al
Accumulator a low words (15-0) bits
9
AH
Accumulator A high character (31-16) bits
A
AG
Acupuna A Protection Locket (39-32 Bit)
B
BL
Accumulator B low word (15-0 bits)
C
BH
Accumulator B high character (31-16 bits)
Di
BG
Accumulator B protection position (39-32 bits)
E
T
Multiplication Register
Fly
TRN
Transfer register
1 0-1 7
AR0-AR7
Auxiliary register ARN N = 0 ~ 7
1 8
SP
Stack pointer
1 9
BK
Cycle buffer size register
1 a
BRC
Block repeat counter
1 b
RSA
Block repeated start address
1 C
REA
Block repeat end address
1 D
PMST
Status register
1 e
XPC
PC extension register
1 e-
1 f
-
Reserve
2 0
BDRR0
Ballless serial port 0 data receiving register
twenty one
BDXR0
Cacked serial port 0 data transmission register
twenty two
BSPC0
Cacked serial port 0 control register
twenty three
BSPCE0
Cacked serial port 0 control extension register
twenty four
Tim
Timer counter
2 5
PRD
Timer cycle register
2 6
TCR
Timer control register
2 7
-
Reserve
2 8
SWWSR
Waiting state generation register
2 9
BSCR
Bank-switching control register
2 a
-
Reserve
2 B
XSWR
Expansion Waiting Status Register
2 c
HPIC
Host Interface Control Register
2 D-
2 f
-
Reserve
3 0
TRCN
TDM serial data receiving register
3 1
TDXR
TDM serial data transmission register
3 2
TSPC
TDM serial port control register
3 3
TCSR
TDM serial channel selection register
3 4
TRTA
TDM serial port receiving send register
3 5
Trad
TDM serial port receiving address register
3 6-3 7
-
Reserve
3 8
AXR0
ABU0 Send Address Register
3 9
BKX0
ABU0 Send Buffer Size Register
3 a
Arr0
ABU0 Receive Address Register
3 B
BKR0
ABU0 Receive Buffer Size Register
3 C
AXR1
ABU1 Send Address Register
3 D
BKX1
ABU1 Send Buffer Size Register
3 e
Arr1
ABU1 Receive Address Register
3 f
BKR1
ABU1 Receive Buffer Size Register
4 0
BDRR1
Ballless serial port 1 data receiving register
4 1
BDXR1
Ballless serial port 1 data send register
4 2
BSPC1
With cache serial port 1 control register
4 3
BSPCE1
With cache serial port 1 control extension register
4 4-5 7
-
Reserve
5 8
CLKMD
Clock mode register
5 9-
5 f
-
Reserve
The following focuses on three state registers
3.3. 1
S t 0 register
The ST0 structure is
l ARP auxiliary register pointer
l TC test / control bit, store the result of the ALU test bit operation, affected by Bit, Bitf, CMPM, CMPR, CMPS, SFTC instruction
L c If the addition is generated in C to 1, subtracting generates borrow C to 0, add instruction
Can only set C, while the SUB instruction can only clear C
l OVA accumulator a overflow sign
l OVB accumulator b overflow logo
l DP data storage space page flag, by the DP specified page, with direct addressing instructions in this page, the absolute address is the high 9-bit plus the direct addressing instructions in the direct addressing instruction for its low 7 bits.
3.3. 2
S t 1 register
The ST1 structure is
l BRAF block repeat indication, BRAF = 1, block repeat operation.
l CPL compiler mode indicating that the relevant direct addressing is used pointer. CPL = 0, use the DP pointer; CPL = 1, use the SP pointer.
l XF indicates an external pin XF state.
l HM suspended, indicating CPU response
The mode of the signal is hm = 0, and the external interface is high; HM = 1, the CPU is stopped.
l INTM global interrupt control bit. INTM = 0, open interrupt; INTM = 1, shielded
Shield interrupt.
l 0 The read value is always 0.
l OVM overflow processing method. Indicates that the processing OVM = 0 in the accumulator is in the occurrence of overflow, the overflow value is constant;
OVM = 1, load forward maximum 007ffffffh or negative maximum 0080000000H.
l SXM symbol extension method, SXM = 0, symbol does not expand; SXM = 1, data is expanded before the ALU used.
L c
16
C
16 = 0 ALU Operation Adopt double precision mode All 32-bit way C16 = 1, ALU operation adopts double 16-bit way.
l FRCT decimal mode, FRCT = 1, and the multiplier output left shift a compensation of excess symbolic bits.
l CMPT compatibility mode, CMPT = 0, ARP is not updated in an indirect addressing method of only single data memory operands, in this manner, the ARP must always be 0; CMPT = 1, ARP is updated under the above conditions, unless Use Ar0.
l ASM accumulator shift number. The shift range 16-15 is specified for parallel storage instructions, STH, STL, ADD, SUB, and LD.
3.3. 3p
MST register
The ST1 structure is:
l IPTR interrupt vector pointer, this 9-bit pointing at the address of the page in the memory space in a page of 128 words. That is, the interrupt vector must be on the beginning of the page. After the reset, IPTR is 1FFH, pointing to the FF80H, redefined to any page.
l
Microcomputer / microprocessor mode
= 0, microcomputer mode, internal ROM accessible;
= 1, microprocessor mode, in-chip ROM is not accessible.
l Ovly Whether the RAM is configured to enter the program space. Ovly = 0, the in-chip RAM is not configured in the program space; OVLY = 1, except 00-7FH, the in-chip RAM is configured to enter the program space. l Avis address display mode, control whether the address data is displayed on the address line when accessing to internal program. AVIS = 0, not displayed; avis = 1, display.
l DROM data ROM configuration, DROM = 0, in-chip ROM is not configured in data space; DROM = 1, partial ROM is configured in data space.
l CLKOFF CLKOUT is closed, CLKOFF = 1, CLKOUT output is forbidden, keep high.
l SMUL multiplication overflow processing. When SMUL = 1, and OVM = 1, FRCT = 1, the operation of the MAC (multiplying) and MAS (multiplying) instruction is based on the ETSI GSM specification, which is reflected in the decimal mode, before subsection / minus. The results of 8000HX8000H are adjusted to 7ffffh, which is equivalent to the MPY ADD instruction in ovm = 1, if only OVM = 1, while SMUL is not 1, only after the addition / minus results, overflow adjustments.
l SST storage overflow processing. When SST = 1, the data in the accumulator is adjusted before the data space is stored. Influencing instructions: Sth, STL, STLM, DSTST || Add, ST || LD, ST || MACR [R], ST || MAS [R], ST || MPY and ST || SUB. Steps:
1) According to the instruction, the data in the accumulator completes left or right.
2) 40 Bacter is adjusted to 32 according to the SXM bit. Bit SXM = 0 (no symbol extension), if the value is greater than 7FFFFFFFH, take 7FFFFFFFH; if SXM = 1 (symbol expansion), if the value is greater than 7FFFFFFH, take 7FFFFFFH, if the value is less than 80000000 hours, take 80000000 hours.
3) Adjust the data to the data space.
4) During the adjustment process, the data in the accumulator does not change.
3.3. 4
Cumulator storage operation
Data storage, AH and Al section in the accumulator are relatively good to accomplish since STH, STL, and STLM. To store content in the AG, you need to use an indirect mode, such as accumulator A.
4. Data addressing
C54x provides seven types of addressing methods:
l immediate addressing
l absolute address addressing
l Cumulator Addressing
l Direct addressing
l Indirect addressing
l Memory Image Register Addressing
l Stack addressing
The following will be introduced in the following ways.
4.1 absolute address addressing
Terminology: DMAD-data storage address; PMAD-program storage address; PA - port address; LK-long integer.
Absolute address addressing includes four categories:
l DMAD addressing
l PMAD addressing
l PA addressing
L * (LK) addressing
4.1.1
D M a D Addressing
DMAD addresses use a label to mark data space addresses, such instructions are:
l MVDK SMEM, DMAD
l MVDM DMAD, MMR
l MVKD DMAD, SMEM
l MVMD MMR, DMAD
Such as: MVKD Sample, * Ar5. Samples here is DMAD.
4.1.2 p
M a D Addressing
PMAD addressing uses a label tag program space address, such instructions are:
l Firs XMEM, YMEM, PMAD
l Macd SMEM, PMAD, SRC
l Macp SMEM, PMAD, SRC
l MVDP SMEM, PMAD
l MVPD PMAD, SMEM
Such as: mvpd table, * ar7- Here, Table is PMAD.
4.1.3 p
A Address
PA Addressing Tags the external I / O port address with a reference numeral, such instructions are:
l PORTR PA, SMEM
l Portw SMEM, PA
Such as: PORTR FIFO, * AR5 This FIFO is PA.
4.1.4
* (LK) addressing
* (LK) Addressing is also marked with the data space address.
Such as: ld * (buffer), a. The benefit of using this type of instruction is not to modify the DP and Ar values. But one thing to note is that such instructions cannot be used to repeat the single instruction (RPT, RPTZ).
4.2 Direct addressing
In such instructions, the address label in the instruction constitutes a low 7 bit (DP mode) of the DMAD or as a forward offset (SP mode), so the address mark in the instruction must not exceed 7. The bit is determined by the CPL bit in ST1.
CPL = 0, using DP; mode CPL = 1, SP mode is used.
4.2.1
DP mode
DP mode, the content in the DP is 9 bits high as the DMAD address, and the address mark in the command is a low 7 bit constitute the DMAD address.
4.2.2
SP mode
SP mode, in the SP as the DMAD base address, the address mark in the instruction is used as the forward offset, and the two additionally constitute the DMAD address.
4.3 Indirect addressing
Indirect addressing means that the DMAD is constructed by the contents of the auxiliary register AR0-AR7. The flexibility to use indirect addressing is not only on one instruction to complete the read or write data storage area (single operating), but also the read operation of two different storage regions, or two different storage regions, or One read operation for two different locations.
4.3.1
Access to S A R A M
Access to Saram Use Register AR0-AR7, where Ar0 is an index register, with the following table:
grammar
Features
description
* ARX
DMAD = ARX
ARX contains DMAD
* ARX-
DMAD = ARX
ARX = ARX-1
After access, the address content in the ARX is 1
* ARX
DMAD = ARX
ARX = ARX 1
Add the address content of the ARX after visiting 1
* ARX
DMAD = ARX 1
ARX = ARX 1
Access before the address content plus 1
* ARX-0B
DMAD = ARX
ARX = B (ARX-AR0)
After the access, the contents of the ARX subtracted in the AR0 and generate reverse borrowing flips (for FFT algorithm)
* ARX-0
DMAD = ARX
ARX = ARX-AR0
After access, the contents of the AR0 will be subtracted in the ARX.
* ARX 0
DMAD = ARX
ARX = ARX AR0
After access, the contents of the ARX subtracted
content
* ARX 0B
DMAD = ARX
ARX = B (ARX AR0)
After access, the contents of the ARX plus the contents in AR0, and generate reverse carry flips (for FFT algorithm) * ARX-%
DMAD = ARX
ARX = CIRC (ARX-1)
After access, the content in the ARX is reduced by loop addressing.
* ARX-0%
DMAD = ARX
ARX = CIRC (ARX-AR0)
After access, the contents of the ARX are subtracted from the contents of the AR0 by loop addressing.
* ARX %
DMAD = ARX
ARX = CIRC (ARX 1)
After access, the contents of the ARX are looped.
Way plus 1
* ARX 0%
DMAD = ARX
ARX = CIRC (ARX AR0)
After access, the contents of the ARX are looped.
Way plus the contents of AR0
* ARX (LK)
DMAD = ARX LK
ARX = ARX
The contents of the ARX plus 16-digit length offset
(LK) is DMAD, ARX is not updated
* ARX (LK)
DMAD = ARX LK
ARX = ARX LK
The contents of the ARX plus 16-digit length offset
(LK) is DMAD, ARX update
* ARX (LK)%
DMAD = CIRC (ARX LK)
ARX = CIRC (ARX LK)
The content in the ARX is plus a loop addressing method.
16-bit long shift (LK) is DMAD, ARX
Update
* (LK)
DMAD = LK
16 absolute address addressing
The loop addressing operation is as follows:
The register BK acts as a loop buffer area (R), and the low n bit of the loop cache base site must be 0, R and N satisfy the following relationship:
, The end address is the base address R, step into value
, Index index is determined by the following algorithm:
4.3.2
Access to D A R A M
Access to DARAM Using Auxiliary Register Ar2-AR5 Used Table:
grammar
Features
description
* ARX
DMAD = ARX
ARX contains DMAD
* ARX-
DMAD = ARX
ARX = ARX-1
After access, the address content in the ARX is 1
* ARX
DMAD = ARX
ARX = ARX 1
After visiting, the address content of the ARX plus 1
* ARX 0%
DMAD = ARX
ARX = CIRC (ARX AR0)
In the case of access, the contents of the AR0 are plus the contents of the AR0 by loop addressing.
5. Interrupt system
Hardware and software drivers can cause C54x to generate interrupt software interrupts, refer to interrupts caused by program instructions, such instructions are: INTR, TRAP, RESET. Hardware interrupts can be triggered by external hardware, or considering inside and outside the slice, whether software interruption or hardware interrupt can be divided into maskable interrupts and immersable interrupts. The C54x processing interrupt is followed by the following:
l Receive interrupt request
l response interrupt
l Execute an interrupt service program
5.1 Interrupt Sign Register I f R (as described in C 5 4 9)
One bit in IFR is 1 indicates that there is a corresponding interrupt again to write 1 clear interrupt
5.2 Interrupt Shield Register I M R (as described in C 5 4 9)
To open an interrupt, simply write 1 bit in the IMR 1 and the INTM bit in ST1 is an interrupt total switch.
5.3 Interrupt location and priority (take C 5 4 9 as an example)
Interrupt number
priority
name
position
Features
0
1
RS / SINTR
0
Reset (hardware and software)
1
2
NMI / SINT16
4
Non-mask interrupt
2
-
SINT17
8
Software interrupt 17
3
-
SINT18
C
Software interrupt 18
4
-
SINT19
10
Software interrupt 19
5
-
Sint20
14
Software interrupt 20
6
-
Sint21
18
Software interrupt 21
Seduce
-
SINT22
1C
Software interrupt 22
8
-
Sint23
20
Software interrupt 23
9
-
Sint24
twenty four
Software interrupt 24
10
-
SINT25
Twist
Software interrupt 25
11
-
SINT26
2C
Software interrupt 26
12
-
Sint27
30
Software interrupt 27
13
-
Sint28
34
Software interrupt 28
14
-
Sint2
38
Software interrupt 29
15
-
SINT30
3C
Software interrupt 30
16
3
INT0 / SINT0
40
External interrupt 0
In one
4
INT1 / SINT1
44
External interrupt 1
18
5
INT2 / SINT2
48
External interrupt 2
19
6
Tint / sint3
4C
Timer interrupt
20
Seduce
Brint0 / sint4
50
Cacked serial port 0 receives interrupt
twenty one
8
BXINT0 / SINT5
54
Ball-up serial port 0 transmission interrupt
twenty two
9
Trint / sint6
58
TDM serial port receiving interrupt
twenty three
10
Txint / sint7
5C
TDM serial port transmission interrupt
twenty four
11
INT3 / SINT8
60
External interrupt 3
25
12
Hint / sint9
64
HPI mouth interrupt
26
13
Brint1 / sint10
68
Ballless serial port 1 receive interrupt
27
14
BXINT1 / SINT11
6C
With cache serial port 1 send interrupt
Twist
15
BMINT0 / SINT14
70
BSP0 past detection interrupt
29
16
BMINT1 / SINT13
74
BSP1 past detection interruption
30-31
-
78
-7f
Reserve
