Machine code instruction code description
37 AAA ASCII adjust AL after additionD5 0A AAD ASCII adjust AX before divisionD5 ib (No mnemonic) Adjust AX before division to number base imm8D4 0A AAM ASCII adjust AX after multiplyD4 ib (No mnemonic) Adjust AX after multiply to number base imm8 3F AAS ASCII adjust AL after subtraction14 ib ADC AL, imm8 Add with carry imm8 to AL15 iw ADC AX, imm16 Add with carry imm16 to AX15 id ADC EAX, imm32 Add with carry imm32 to EAX80 / 2 ib ADC r / m8, imm8 Add with carry imm8 TO R / M16, IMM16 Add with Carry IMM16 TO R / M1681 / 2 ID ADC R / M32, IMM32 Add with CF IMM32 TO R / M3283 / 2 IB ADC R / M16, IMM8 Add with CF SIGN-EXTENDED IMM8 TO R / M1683 / 2 IB ADC R / M32, IMM8 Add with CF Sign-Extended IMM8 INTO R / M3210 / R ADC R / M8, R8 Add with Carry Byte Register TO R / M811 / R ADC R / M16, R16 Add with Carry R16 TO R / M1611 / R ADC R / M32, R32 Add with CF R32 TO R / M3212 / R ADC R8, R / M8 Add with Carry R / M8 to Byte Register13 / R ADC R16, R / M16 Add with Carry R / M16 TO R1613 / R ADC R32, R / M32 Add with CF R / M32 TO R3204 IB ADD AL, IMM8 Add IMM8 TO AL05 IW AX, IMM16 ADD IMM16 TO AX05 ID ADD Eax, IMM32 ADD IMM32 TO EAX80 / 0 IB ADD R / M8,
IMM8 Add IMM8 TO R / M16, IMM16 ADD IMM16 TO R / M1681 / 0 ID ADD R / M32, IMM32 ADD IMM32 TO R / M3283 / 0 Ib ADD R / M16, IMM8 Add Sign-Exteden IMM8 TO R / M1683 / 0 IB ADD R / M32, IMM8 Add Sign-Extended IMM8 TO R / M3200 / R ADD R / M8, R8 ADD R / M16, R16 ADD R16 TO R / M1601 / R ADD R / M32, R32 ADD R32 TO R / M3202 / R ADD R8, R / M8 ADD R / M8 TO R803 / R ADD R / M8 TO R160 / R ADD R32, R / M32 Add R / M32 TO R3266 0F 58 / R AddPD XMM1, XMM2 / M128 Add Packed Double-Precision Floating-Point Values from XMM2 / M128 TO XMM1.0F 58 / R AddPS XMM1, XMM2 / M128 Add Packed Single-Precision Floating- Point Values from XMM2 / M128 TO XMM1.F2 0F 58 / R Addsd XMM1, XM M2 / M64 Add The Low Double-Precision Floating-Point Value from xmm2 / m64 to xmm1.f3 0f 58 / r adds xmm1, xmm2 / m32 add the low single-precision floating-point value from xmm2 / m32 to xmm1.24 ib And Al, IMM8 Al and IMM825 IW and AX, IMM16 AX and IMM1625 ID AND Eax, IMM32 Eax and IMM3280 / 4 IB And R / M8, IMM8 R / M8 AND IMM881 / 4 IW AND R / M16, IMM16 R / M16 AND IMM1681 / 4 ID AND R / M32, IMM32 R / M32 and IMM3283 / 4 IB and R / M16, IMM8 R / M16 AND IMM8 (SIGN-EXTENDED 83/4 IB and R / M32,
IMM8 R / M32 and IMM8 (SIGN-EXTENDED) 20 / R and R / M8, R8 R / M8 AND R821 / R AND R / M16, R16 R / M16 AND R1621 / R AND R / M32, R32 R / M32 AND R3222 / R and R / M823 / R AND R16, R / M16 R16 AND R / M1623 / R AND R32, R / M32 R32 AND R / M3266 0F 54 / R ANDPD XMM1, XMM2 / M128 Bitwise Logical and Of Of 54 / R Andps XMM1, XMM2 / M128 Bitwise Logical And Of XM2 / M128 and XMM1.66 0F 55 / R andNPD XMM1, XMM2 / M128 Bitwise Logical and Not Of XMM2 / M128 and NOT XMM1.0F 55 / R andNPS XMM1, XMM2 / M128 Bitwise Logical and NOT OF XMM2 / M128 and XMM1.63 / R Arpl R / M16, R16 Adjust RPL of R / M16 to Not Less Than RPL of R1662 / R Bound R16, M16 & 16 Check IF R16 (Array Index) IS WITHIN BOUNDS Specified by M16 & 1662 / R Bound R32, M32 & 32 Check IF R32 (Array Index) IS WITHIN BOUNDS Specified by M16 & 160F BC BSF R16, R / M16 Bit Scan Forward On R / M160F BC BSF R32, R / M32 Bit Scan Forward On R / M320F BD BSR R16, R / M16 Bit Scan Reverse On R / M160F BD BSR R32, R / M32 Bit Scan Reverse On R / M320F C8 RD Bswap R32 Reverses The Byte ORDER OF A 32-BIT Register.0f A3 BT R / M16, R16 Store Selected Bit In CF Flag0f A3 BT R / M32, R32 Store SELECTED BIT IN CF FLAG0F BA / 4 IB BT R / M16, IMM8 Store Selected Bit In CF Flag0F BA / 4 IB BT R / M32,
imm8 Store selected bit in CF flag0F BB BTC r / m16, r16 Store selected bit in CF flag and complement0F BB BTC r / m32, r32 Store selected bit in CF flag and complement0F BA / 7 ib BTC r / m16, imm8 Store selected bit In CF Flag and Complement0F BA / 7 IB BTC R / M32, IMM8 Store Selected Bit IN CF Flag and Complement0f B3 BTR R / M16, R16 Store Selected Bit In CF Flag and Clear0f B3 BTR R / M32, R32 Store Selected Bit In CF Flag and Clear0F BA / 6 IB BTR R / M16, IMM8 Store Selected Bit In CF Flag and Clear0F BA / 6 IB BTR R / M32, IMM8 Store Selected Bit In CF Flag and Clear0f Ab BTS R / M16, R16 Store Selected Bit in CF flag and set0f ab bts r / m32, r32 store selected bit in cf flag and set0f ba / 5 IB BTS R / M16, IMM8 Store SELECTED BIT IN CF FLAG AND SE0F BA / 5 IB BTS R / M32, IMM8 Store selected bit in CF flag and setE8 cw CALL rel16 Call near, relative, displacement relative to next instructionE8 cd CALL rel32 Call near, relative, displacement relative to next instructionFF / 2 CALL r / m16 Call near, absolute indirect, address given in r / M16FF / 2 Call R / M32 Call Near, Absolute Indirect, Address Given In R / M329A CD CALL PTR16: 16 Call Far, Absolute, Address Given In Operand9a CP Call Ptr16: 32 Call Far, Absolute,
address given in operandFF / 3 CALL m16: 16 Call far, absolute indirect, address given in m16: 16FF / 3 CALL m16: 32 Call far, absolute indirect, address given in m16: 3298 cb W AX ← sign-extend of AL98 CWDE EAX ← sign-extend of AXF8 CLC Clear CF flagFC CLD Clear DF flag0F AE / 7 CLFLUSH m8 Flushes cache line containing m8.FA CLI Clear interrupt flag; interrupts disabled when interrupt flag cleared0F 06 CLTS Clears TS flag in CR0F5 CMC Complement CF flag0F 47 / R CMOVA R16, R / M16 MOVE IF ABOVE (CF = 0 and zf = 0) 0F 47 / R CMOVA R32, R / M32 Move IF Above (CF = 0 and ZF = 0) 0F 43 / R CMOVAE R16, R / m16 m Ove if Above or equal (cf = 0) 0F 43 / R CMOVAE R32, R / M32 MOVE IF ABOVE OR Equal (CF = 0) 0F 42 / R CMOVB R16, R / M16 MOVE IF BELOW (CF = 1) 0F 42 / R CMOVB R32, R / M32 MOVE IF BELOW (CF = 1) 0F 46 / R CMOVBE R16, R / M16 MOVE IF BEQUAL (CF = 1 or ZF = 1) 0F 46 / R CMOVBE R32, R / M32 Move if Below or equal (cf = 1 or zf = 1) 0F 42 / r CMOVC R16, R / M16 Move IF Carry (CF = 1) 0F 42 / R CMOVC R32, R / M32 Move IF Carry (CF = 1) 0F 44 / R CMOVE R16, R / M16 MOVE IF Equal (zf = 1) 0F 44 / R CMOVE R32, R / M32 Move IF Equal (ZF = 1) 0F 4F / R CMOVG R16,
R / M16 Move if Greater (zf = 0 and sf = of) 0f 4f / r CMOVG R32, R / M32 Move if Greater (zf = 0 and sf = of) 0f 4D / R CMOVGE R16, R / M16 MOVE IF Greater OR Equal (sf = of) 0F 4D / R CMOVGE R32, R / M32 MOVE IF Greater OR Equal (sf = of) 0F 4C / R CMOVL R16, R / M16 MOVE IF LESS (SF <> of) 0F 4C / R CMOVL R32, R / M32 MOVE IF LESS (SF <> of) 0F 4e / R CMOVLE R16, R / M16 MOVE IF <> of) 0F 4E / R CMOVLE R32, R / M32 Move if Less or Equal (zf = 1 or sf <> of) 0F 46 / R CMOVNA R16, R / M16 Move if Not Above (CF = 1 or ZF = 1) 0F 46 / R CMOVNA R32, R / M32 MOVE IF NOT ABOVE (CF = 1 or zf = 1) 0F 42 / R CMOVNAE R16, R / M16 Move if Not Above or Equal (cf = 1) 0F 42 / R CMOVNAE R32, R / M32 MOVE IF NOT ABOVE OR Equal (CF = 1) 0F 43 / R CMOVNB R16, R / M16 Move IF Not Below (CF = 0) 0F 43 / R CMOVNB R32, R / M32 Move IF Not Below (CF = 0) 0F 47 / R CMOVNBE R16, R / M16 MOVE IF NOT BELOW OR Equal (CF = 0 and ZF = 0) 0F 47 / R CMOVNBE R32, R / M32 MOVE IF NOT BELOW OR Equal (CF = 0 and ZF = 0) 0f 43 / R CMOVNC R16, R / M16 MOVE IF NOT Carry (CF = 0) 0F 43 / R CMOVNC R32, R / M32 Move IF Not Carry (CF = 0) 0F 45 / R CMOVNE R16, R / M16 MOVE IF NOT Equal (zf = 0) 0F 45 / R CMOVNE R32, R / M32 MOVE IF NOT EQUAL (ZF = 0) 0F 4e / R CMOVNG R16, R / M16 Move if Not Greater (ZF = 1 or sf <> of) 0F 4E / R CMOVNG R32,
R / M32 MOVE IF NOT GREATER (ZF = 1 or sf <> of) 0F 4C / R CMOVNGE R16, R / M16 MOVE IF NOT GREATER OR Equal (SF <> of) 0F 4C / R CMOVNGE R32, R / M32 MOVE IF Not Greater or Equal (s> of) 0F 4D / R CMOVNL R16, R / M16 MOVE IF NOT (SF = of) 0F 4D / R CMOVNL R32, R / M32 MOVE IF Not Less (sf = of) 0F 4F / R CMOVNLE R16, R / M16 MOVE IF NOT IL Equal (zf = 0 and sf = of) 0F 4F / R CMOVNLE R32, R / M32 MOVE IF NOT INTOR Equal (zf = 0 and sf = of) 0f 41 / R CMOVNO R16, R / M16 MOVE IF NOT OVERFLOW (OF = 0) 0F 41 / R CMOVNO R32, R / M32 MOVE IF NOT OVERFLOW (= 0) 0F 4B / R CMOVNP R16, R / M16 MOVE IF NOT PARITY (PF = 0) 0F 4B / R CMOVNP R32, R / M32 Move IF Not Parity (PF = 0) 0F 49 / R CMOVNS R16, R / M16 MOVE IF NOT SIGN (SF = 0) 0F 49 / R CMOVNS R32 , R / M32 MOVE IF NOT SIGN (SF = 0) 0F 45 / R CMOVNZ R16, R / M16 MOVE IF NOT ZERO (ZF = 0) 0F 45 / R CMOVNZ R32, R / M32 MOVE IF NOT ZERO (ZF = 0) 0F 40 / R CMOVO R16, R / M16 Move IF overflow (= 0) 0F 40 / R CMOVO R32, R / M32 Move IF overflow (= 0 ) 0F 4A / R CMOVP R16, R / M16 Move IF PARITY (PF = 1) 0F 4A / R CMOVP R32, R / M32 Move IF PARITY (PF = 1) 0F 4A / R CMOVPE R16, R / M16 MOVE IF PARITY EVEN (PF = 1) 0F 4A / R CMOVPE R32, R / M32 MOVE IF PARITY EVEN (PF = 1) 0F 4B / R CMOVPO R16, R / M16 Move IF Parity ODD (PF = 0) 0F 4B / R CMOVPO R32 , R / M32 Move IF Parity ODD (PF = 0) 0F 48 / R CMOVS R16,
R / M16 MOVE IF SIGN (SF = 1) 0F 48 / R CMOVS R32, R / M32 MOVE IF SIGN (SF = 1) 0F 44 / R CMOVZ R16, R / M16 MOVE IF ZERO (ZF = 1) 0F 44 / R Movz R32, R / M32 Move IF Zero (ZF = 1) 3C IB CMP Al, IMM8 Compare Imm8 with Al3D IW CMP AX, IMM16 Compare Imm16 with AX3D ID CMP Eax, IMM32 Compare Imm32 with EAX80 / 7 IB CMP R / M8 , IMM8 COMPARE IMM8 with R / M881 / 7 IW CMP R / M16, IMM16 COMPARE IMM16 with R / M1681 / 7 ID CMP R / M32, IMM32 COMPARE IMM32 WITH R / M3283 / 7 IB CMP R / M16, IMM8 Compare Imm8 with R / M1683 / 7 IB CMP R / M32, IMM8 COMPARE IMM8 with R / M3238 / R CMP R / M8, R8 COMPARE R8 WITH R / M839 / R CMP R / M16, R16 COMPARE R16 WITH R / M1639 / R CMP R / M32, R32 COMPARE R32 with R / M323A / R CMP R8, R / M8 COMPARE R / M8 with R83B / R CMP R16, R / M16 COMPARE R / M16 WITH R163B / R CMP R32, R / M32 COMPARE R / M32 WITH R3266 0F C2 / R IB CMPPD XMM1, XMM2 / M128, IMM8 COMPARE PACKED DOUBLE-PRECISION FLOATING-POINT VALUES in xmm2 / m128 and xmm1 using imm8 as comparison predicate.0F C2 / r ib CMPPS xmm1, xmm2 / m128, imm8 Compare packed single-precision floating-point values xmm2 / mem and xmm1 using imm8 as comparison predicate.A6 CMPS m8,
M8 Compares Byte At Address DS: (e) Si with Byte At Address ES: (E) DI AND Sets The Status Flags Accordinglya7 CMPS M16, M16 Compares Word At Address DS: (E) Si with Word At Addresses: (E) DI and SETs the status flags accordinglyA7 CMPS m32, m32 Compares doubleword at address DS: (E) SI with doubleword at address ES: (E) DI and SETs the status flags accordinglyA6 CMPSB Compares byte at address DS: (E) SI with byte at Address ES: (E) DI AND STS The Status Flags Accordinglya7 Cmpsw Compares Word At Address DS: (E) Si with word at address ES: (E) DI and sets the status flags accordinglyA7 CMPSD Compares doubleword at address DS: (E) SI with doubleword at address ES: (E) DI and SETs the status flags accordinglyF2 0F C2 / r ib CMPSD xmm1, XMM2 / M64, IMM8 Compare Low Double-Precision Floating-Point Value In XMM2 / M64 and XMM1 Using Imm8 As Comparison Predicate.f3 0F C2 / R IB CMPSS XMM1, XMM2 / M32,
IMM8 Compare Low Single-Precision Floating-Point Value in XMM2 / M32 and XMM1 Using IMM8 AS Comparison Predicate.0F B0 / R CMPXCHG R / M8, R8 Compare Al with R / M8. if Equal, ZF IS SET AND R8 is loaded INTO R / m8. Else, Clear ZF AND LOAD R / M8 INTO Al.0F B1 / R CMPXCHG R / M16, R16 COMPARE AX with R / M16. IF Equal, ZF IS SET AND R16 IS LOADED INTO R / M16. ELSE, CLEAR ZF AND LOAD R / M16 INTO AL0F B1 / R CMPXCHG R / M32, R32 Compare Equal, ZF IS SET AND R32 IS LOADED INTO R / M32. Else, Clear Zf and LOAD R / M32 INTO Al0F C7 / 1 M64 CMPXCHG8B M64 COMPARE EDX: EQUAL, SET ZF AND LOAD ECX: EBX INTO M64. Else, Clear Zf and Load M64 INTO EDX: EAX.66 0F 2F / R COMISD XMM1, XMM2 / M64 Compare Low Double-Precision Floating-Point Values in XMM1 and XMM2 / MEM64 and SET The EFLAGS flags accountingly.0f 2f / r COMISS XMM1,
xmm2 / m32 Compare low single-precision floating-point values in xmm1 and xmm2 / mem32 and set the EFLAGS flags accordingly.0F A2 CPUID Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, according to the input value entered initially in the EAX registerF3 0F E6 CVTDQ2PD xmm1, xmm2 / m64 Convert two packed signed doubleword integers from xmm2 / m128 to two packed double-precision floating-point values in xmm1.0F 5B / r CVTDQ2PS xmm1, xmm2 / m128 Convert four Packed Signed DoubleWord Integers from xmm2 / m128 to four packed salesle-precision floating-point values in xmm1.F2 0F E6 CVTPD2DQ xmm1, xmm2 / m128 Convert two packed double-precision floating-point values from xmm2 / m128 to two packed signed doubleword integers in xmm1.66 0F 2D / r CVTPD2PI mm, xmm / m128 Convert Two Packed Double-Precision Floating-Point Values from XMM / M128 To Two Packed Signed Doubleword Integers in mm.66 0f 5A / R CVTPD2PS XMM1,
xmm2 / m128 Convert two packed double-precision floating-point values in xmm2 / m128 to two packed single-precision floating-point values in xmm1.66 0F 2A / r CVTPI2PD xmm, mm / m64 Convert two packed signed doubleword integers from mm / mem64 to two packed double-precision floating-point values in xmm.0F 2A / r CVTPI2PS xmm, mm / m64 Convert two signed doubleword integers from mm / m64 to twosingle-precision floating-point values in xmm..66 0F 5B / r CVTPS2DQ xmm1, xmm2 / m128 Convert four packed single-precision floating-point values from xmm2 / m128 to four packed signed doubleword integers in xmm1.0F 5A / r CVTPS2PD xmm1, xmm2 / m64 Convert two packed single-precision f loating-point values in xmm2 / m64 to two packed double-precision floating-point values in xmm1.0F 2D / r CVTPS2PI mm, xmm / m64 Convert two packed single-precision floating-point values from xmm / m64 to two packed signed doubleword Integers in mm.f2 0f 2d / r CVTSD2SI R32, XMM / M64 Convert One Double-Precision Floating-Point Value from XMM / M64 To One Signed DoubleWord Integer R32.f2 0F 5A / R CVTSD2SS XMM1,
xmm2 / m64 Convert one double-precision floating-point value in xmm2 / m64 to one single-precision floating-point value in xmm1.F2 0F 2A / r CVTSI2SD xmm, r / m32 Convert one signed doubleword integer from r / m32 to one double-precision floating-point value in xmm.F3 0F 2A / r CVTSI2SS xmm, r / m32 Convert one signed doubleword integer from r / m32 to one single-precision floating-point value in xmm.F3 0F 5A / r CVTSS2SD xmm1, xmm2 / m32 Convert one single-precision floating-point value in xmm2 / m32 to one double-precision floating-point value in xmm1.F3 0F 2D / r CVTSS2SI r32, xmm / m32 Convert one single-precision floating-point value from xmm / m32 to one signed Doublewo rd integer in r32.66 0F 2C / r CVTTPD2PI mm, xmm / m128 Convert two packer double-precision floating-point values from xmm / m128 to two packed signed doubleword integers in mm using truncation.66 0F E6 CVTTPD2DQ xmm1, xmm2 / m128 Convert Two Packed Double-Precision Floating-Point Values from XMM2 / M128 To Two Packed Signed Doubleword INTEGERS in Xmm1 Using Truncation.f3 0F 5B / R CVTTPS2DQ XMM1,
xmm2 / m128 Convert four single-precision floating-point values from xmm2 / m128 to four signed doubleword integers in xmm1 using truncation.0F 2C / r CVTTPS2PI mm, xmm / m64 Convert two single-precision floating-point values from xmm / m64 to two signed doubleword signed integers in mm using truncation.F2 0F 2C / r CVTTSD2SI r32, xmm / m64 Convert one double-precision floating-point value from xmm / m64 to one signed doubleword integer in r32 using truncation.F3 0F 2C / r CVTTSS2SI R32, XMM / M32 Convert One Single-Precision Floating-Point Value from XMM / M32 To One Signed Doubleword INTEGER IN R32 Using TRUNCATION.99 CW Dx: AX ← SIGN-EXTEND OF AX99 CDQ EDX: EX ← SIGND OF EAX27 DAA DECIMAL Adjust Al After ADDITION2F DAS DECIMAL Adjust Al After Subtractionfe / 1 DEC R / M8 DECREMENT R / M8 BY 1FF / 1 DEC R / M16 Decrement R / M16 by 1F / 1 DEC R / M32 Decrement R / M32 by 148 RW DEC R16 Decrement R16 by 148 RD DEC R32 Decrement R32 by 1F6 / 6 DIV R / M8 Unsigned Divide AX by R / M8, with Result Stored in AL ← Quotient,
AH ← RemainDERF7 / 6 DIV R / M16 Unsigned Divide DX: AX by r / m16 EAX ← Quotient, EDX ← Remainder66 0F 5E / r DIVPD xmm1, xmm2 / m128 Divide packed double-precision floating-point values in xmm1 by packed double-precision floating-point values in xmm2 / m128.0F 5E / r DIVPS xmm1, xmm2 / m128 Divide packed single-precision floating-point values in xmm1 by packed single-precision floating-point values in xmm2 / m128.F2 0F 5E / r DIVSD xmm1, xmm2 / m64 Divide low double-precision floating-point value in xmm1 by low double-precision floating-point value in xmm2 / mem64.F3 0F 5E / r DIVSS xmm1, xmm2 / m32 Divide low single-precision floating-point value in xmm1 by low single-precision floating-point value in xmm2 / m320F 77 EMMS Set the x87 fpu tag word to empty.c8 ing 00 Enter Imm16,0 create a stack frame for a procedurec8 IW 01 ENTER IMM16, 1 CREATE A NESTED Stack Frame for a procedurec8 IW ib ENTER IMM16,
IMM8 Create A Nested9 F0 FRAME for a Procedure ST (0) with (2 ^ st (0) 1) D9 E1 FABS Replace St with ITS ABSOLUTE VALUE.D8 / 0 FADD M32FP Add M32FP To St (0) And Store Result in st (0) DC / 0 FADD M64FP Add M64FP to St (0) And Store Result in St (0) D8 C0 I Fadd St (0), ST (I) Add St (0) TO ST (i) And Store Result in St (0) DC C0 I Fadd St (I), ST (0) Add St (I) TO ST (0) And Store Result In St (i) DE C0 I Faddp St (i), ST (0) Add st (0) To St (i), Store Result In St (I), AND POP The Register Stackde C1 Faddp Add St (0) To St (1), Store Result In St (1),
And pop The register stackda / 0 FIADD M32INT ADD M32INT TO ST (0) And Store Result in St (0) DE / 0 FIADD M16INT Add M16INT TO ST (0) And Store Result In St (0) DF / 4 FBLD M80 DEC Convert bcd value to floating-point and push oto the fpu stack.df / 6 fbstp m80bcd store st (0) in m80bcd and pop st (0) .d9 E0 FCHS Complements SIGN OF ST (0) 9B DB E2 FCLEX CLEAR FLOATING- point exception flags after checking for pending unmasked floating-point exceptions.DB E2 FNCLEX * Clear floating-point exception flags without checking for pending unmasked floating-point exceptions.DA C0 i FCMOVB ST (0), ST (i) Move if below (CF = 1) DA C8 I FCMOVE ST (0), ST (I) Move if Equal (zf = 1) DA D0 I fcmovbe st (0), ST (i) Move if Below or equal (cf = 1 or zf = 1) DA D8 I FCMOVU ST (0), ST (i) Move if unordered (PF = 1) DB C0 I fcmovnb st (0), ST (i) Move if not below (cf = 0) DB C8 I fcmovne st (0), ST (i) Move if not equal (zf = 0) DB DB DB D0 I FCMOVNBE ST (0), ST (I) Move if Not Below or Equal (CF = 0 and zf = 0) DB D8 I FCMOVNU ST (0),
ST (i) Move if not unordered (pf = 0) D8 / 2 FCOM M32FP Compare St (0) with m32fp.dc / 2 FCOM M64FP Compare St (0) with m64fp.d8 d0 i fcom st (i) Compare St (0) with st (i) .d8 d1 fcom compare st (0) with st (1) .d8 / 3 FCOMP M32FP Compare St (0) with m32fp and pop register stack.dc / 3 fcomp m64fp compare st (0) With m64fp and pop register stack.d8 d8 i fcomp st (i) compare st (0) with st (i) and pop register stack.d8 d9 fcomp compare st (0) with st (1) and pop register stack.de D9 FCOMPP Compare St (0) with st (1) And Pop Register Stack TWICE.DB F0 I FCOMI ST, ST (I) Compare St (0) with st (i) and set status flags accountinglydf f0 i fcomip st, ST (i) Compare St (0) with St (I), SET Status Flags Accordingly, And Pop Register StackDB E8 I FUCOMI ST, ST (I) Compare St (0) with St (i), Check for Ordered Values, And Set Status Flags AccordinglyDF E8 I FUCOMIP ST, ST (I) Compare St (0) with St (i), Check for Ordered Values, Set Status Flags Accordingly,
and pop register stackD9 FF FCOS REPlace ST (0) with its cosineD9 F6 FDECSTP Decrement TOP field in FPU status word.D8 / 6 FDIV m32fp Divide ST (0) by m32fp and store result in ST (0) DC / 6 FDIV m64fp Divide ST (0) by M64FP and Store Result in St (0) D8 F0 I fdiv st (0), ST (i) Divide St (0) by St (i) and store results in st (0) DC F8 i FDIV ST (I), ST (0) Divide St (i) by St (0) And Store Result In St (i) DE F8 I FDIVP ST (I), ST (0) Divide St (i) by ST ( 0), Store Result in St (I), AND POP The Register Stackde F9 fdivp Divide St (1) BY ST (0), Store Result in St (1), And Pop The Register StackDA / 6 FIDIV M32Int Divide St (0 ) by m32int and store results in st (0) DE / 6 FIDIV M16INT DIVIDE ST (0) B Y M64INT and Store Result in St (0) D8 / 7 FDIVR M32FP Divide M32FP by St (0) And Store Result in St (0) DC / 7 FDIVR M64FP DIVIDE M64FP BY ST (0) And Store Result in St (0) D8 F8 I fdiVR ST (0), ST (i) Divide St (i) by st (0) and store results in st (0) DC F0 I fdiVR ST (I), ST (0) Divide St (0 ) by ST (i) and store results in st (i) de f0 i fdivrp st (i), st (0) Divide St (0) by St (i), Store Result in St (i), and Pop the Register stackde f1 fdivrp divide st (0) by st (1), Store Result in St (1),
And pop The register s on st (0) DD c0 i ffree st (0) DD C0 I ffree st (0) DD C0 I FFree ST (i) sets tag for st (i) to Emptyde / 2 FICOM M16INT COMPARE ST (0) with m36intda / 2 FICOM M32INT COMPARE ST (0) with m32intde / 3 FICMP M16INT Compare St (0) with m16int and pop stack registerDA / 3 FICOMP m32int Compare ST (0) with m32int and pop stack registerDF / 0 FILD m16int Push m16int onto the FPU register stack.DB / 0 FILD m32int Push m32int onto the FPU register stack.DF / 5 FILD m64int Push m64int onto the FPU register Stack.d9 F7 FincStp Increment The Top Field in The FPU Status Register9b DB E3 Finit Initialize FPU Afte r checking for pending unmasked floating-point exceptions.DB E3 FNINIT * Initialize FPU without checking for pending unmasked floating-point exceptions.DF / 2 FIST m16int Store ST (0) in m16intDB / 2 FIST m32int Store ST (0) in m32intDF / 3 fistp m16int store st (0) in m16int and pop register store st (0) in m32int and pop register store st (0) in m64int and pop register stackd9 / 0 FLD M32FP PUSH
M32FP ONTO THE FPU REGISTER Stack.dd / 0 FLD M64FP PUSH M64FP ONTO THE FPU REGISTER Stack.db / 5 FLD M80FP PUSH M80FP ONTO THE FPU Register Stack.d9 C0 I FLD St (i) Push St (i) ONTO THE FPU register stack.D9 E8 FLD1 Push 1.0 onto the FPU register stack.D9 E9 FLDL2T Push log2 10 onto the FPU register stack.D9 EA FLDL2E Push log2 e onto the FPU register stack.D9 EB FLDPI Push PI onto the FPU register stack. D9 EC FLDLG2 Push log10 2 onto the FPU register stack.D9 ED FLDLN2 Push loge 2 onto the FPU register stack.D9 EE FLDZ Push 0.0 onto the FPU register stack.D9 / 5 FLDCW m2byte Load FPU control word from m2byte.D9 / 4 Fldenv M14 / 28Byte Load FPU Environment from M14byte or m28byte.d8 / 1 fmul m32fp multiply st (0) by m32fp and store results in st (0) DC / 1 Fmul M64fp multiply st (0) by m64fp and store results in st (0) D8 C8 I Fmul ST (0), ST (I) Multiply St (0) by St (i) and store results in st (0) DC C8 I Fmul St (i), st (0) Multiply St (i) by st (0) And Store Result In St (I) DE C8 I Fmulp St (I), St (0) Multiply St (i) by St (0), Store Result In St (I), AND POP The Register Stackde C9 Fmulp Multiply ST (1) BY ST (0), Store Result in St (1), And Pop The Register StackDA / 1
Fimul m32int multiply st (0) DE / 1 FIMUL M16INT MULTIPLY ST (0) by m16int and store result in st (0) D9 d0 fnop no Operation is perform St.d9 f3 fpatan replace ST (1) with arctan (st (1) st (0)) and pop the register stackd9 f8 fprem replace st (0) with the remain ketage td from dividing st (0) by st (1) D9 f5 fprem1 replace st (0) With the IEEE Remainder Obtained from Dividing St (0) by St (1) D9 F2 FPTAN Replace St (0) with ITS TANGENT AND PUSH 1 ONTO THE FPU Stack.d9 fc frndint round st (0) to an inTeger.dd / 4 FRSTOR M94 / 108BYTE LOAD FPU State from M94Byte OR M108B yte.9B DD / 6 FSAVE m94 / 108byte Store FPU state to m94byte or m108byte after checking for pending unmasked floating-point exceptions. Then re-initialize the FPU.DD / 6 FNSAVE * m94 / 108byte Store FPU environment to m94byte or m108byte without CHECKING FOR PENDING UNMASKED FLOATING-POINT Exceptions. Then re-initialize the fpu.d9 fd fscale scale st (0) by st (1) .d9 fe fsin replace st (0) with it.d9 fb fsincos compute the sine and cosine Of St (0);
Replace st (0) with the register stack.d9 fa fsqrt computes square root of st (0) and store result in st (0) D9 / 2 FST M32FP COPY ST (0) TO M32FPDD / 2 FST M64FP COPY ST (0) TO M64FPDD D0 I FST ST (I) Copy St (0) TO ST (I) D9 / 3 FSTP M32FP COPY ST (0) TO M32FP AND POP Register StackDD / 3 FSTP M64FP COPY ST (0) to m64fp and pop register stackDB / 7 FSTP M80FP COPY ST (0) TO M80FP AND POP Register StackDD D8 I FSTP ST (I) Copy St (0) TO ST (I) AND POP Register Stack9b D9 / 7 FSTCW M2byte Store FPU Control Word To M2byte After Checking for Pending Unmasked Floating-Point Exceptions.d9 / 7 Fnstcw * M2byte Store FPU control word to m2byte without checking for pending unmasked floating-point exceptions.9B D9 / 6 FSTENV m14 / 28byte Store FPU environment to m14byte or m28byte after checking for pending unmasked floating-point exceptions. Then mask all floating-point exceptions.D9 / 6 FNStenv * M14 / 28Byte Store FPU Environment To M14byte OR M28BYTE WITHOUT CHECKING FL PENDING UNMASKED FLOATING-POINT Exceptions. The Mask All Floating-Point Exceptions.9b D
D / 7 FSTSW m2byte Store FPU status word at m2byte after checking for pending unmasked floating-point exceptions.9B DF E0 FSTSW AX Store FPU status word in AX register after checking for pending unmasked floating-point exceptions.DD / 7 FNSTSW * m2byte Store FPU status word at m2byte without checking for pending unmasked floating-point exceptions.DF E0 FNSTSW * AX Store FPU status word in AX register without checking for pending unmasked floating-point exceptions.D8 / 4 FSUB m32fp Subtract m32fp from ST (0) and Store Result in St (0) DC / 4 FSUB M64FP Subtract M64FP from St (0) And Store Result In St (0) D8 E0 I FSUB ST (0), ST (I) Subtract St (i) from St (0 ) And Store Resul T in st (0) DC E8 I FSUB ST (I), ST (0) SUBTRACT ST (0) from St (i) AND Store Result in St (i) de E8 I FSUBP ST (I), ST ( 0) Subtract St (0) from St (I), Store Result In St (I), AND POP Register Stackde E9 FSUBP SUBTRACT ST (0) from St (1), Store Result In St (1), and Pop Register StackDA / 4 FISUB M32INT SUBTRACT M32INT from St (0) DE / 4 FISUB M16INT Subtract M16INT from St (0) And Store Result in St (0) D8 / 5 FSUBR M32FP Subtract St (0) from M32FP and Store Result in St (0) DC / 5 FSUBR M64FP
Subtract St (0) from M64FP and Store Result in St (0) D8 E8 I FSUBR ST (0), ST (I) Subtract St (0) from St (i) And Store Result in St (0) DC E0 I Fsubr ST (I), ST (0) Subtract St (I) from St (0) And Store Result In St (i) DE E0 I FSUBRP ST (I), ST (0) Subtract St (i) from ST (0), Store Result in St (I), AND POP Register Stackde E1 Fsubrp Subtract St (1) from Store Result In St (1), And Pop Register StackDA / 5 FISUBR M32INT SUBTRACT ST (0) From m32int and store results in st (0) DE / 5 FISUBR M16INT Subtract St (0) from m16int and store results in st (0) D9 E4 ftst compare st (0) with 0.0.dd E0 I FUCOM ST (i) Compare St (0) with St (i) DD E1 FUCOM Compare St (0) with st (1) DD E8 I Fucomp St (i) Compare ST (0 ) with st (i) and pop register st (0) with st (1) And pop register st (0) with st (1) and pop register stack twiced9 E5 fxam classify value or number in ST (0) D9 C8 I FXCH ST (I) Exchange The Contents of St (0) And St (i) D9 C9 FXCH Exchange The Contents of St (0) and st (1) 0f AE / 1 FXRStor M512byte Restore THE X87 FPU, MMX, XMM, AND MXCSR Register State from M512byte.0F AE / 0 FXSAVE M512BYTE SAVE THE X87 FPU, MMX, XMM, AND MXCSR Register
St (0) INTO EXPONENT AND SIGNIFICAND, Store Exponent And Significand, Store Exponent In St (0), And Push The Significand ONTO THE REGISTER Stack.d9 F1 FYL2X Replace St (1) with (ST (1) * log2st (0)) and pop the register stackd9 f9 fyl2xp1 replace st (1) with st (1) * log2 (st (0) 1.0) and pop the register stackf4 hlt haltf6 / 7 IDIV R / M8 Signed Divide Ax by R / M8, with result stiled in al ← quotient, AH ← RemainDERF7 / 7 IDIV R / M16 Signed Divide DX: AX by R / M16, with Result Stored in AX ← Quotient, DX ← RemainDERF7 / 7 IDIV R / M32 Signed Divide Edx: EAX BY R / M32, with Result Stored in Eax ← Remainderf6 / 5 Imul R / M8 AX ← Al * R / m Bytef7 / 5 Imul R / M16 DX: AX ← AX * R / M Wordf7 / 5 Imul R / M32 EDX: EAX ← EAX * R / M DOUBLEWORD0F AF / R IMUL R16, R / M16 Word Register ← Word Register * R / M Word0F AF / R IMUL R32, R / M32 Doubleword Register ← Doubleword Register * R / m DoubleWord6b / R IB Imul R16, R / M16, IMM8 Word Register ← R / M16 * Sign-Extended Immediate Byte6B / R IB Imul R32, R / M32, IMM8 DoubleWord Register ← R / M32 * Sign-Exteden
immediate byte6B / r ib IMUL r16, imm8 word register ← word register * sign-extended immediate byte6B / r ib IMUL r32, imm8 doubleword register ← doubleword register * sign-extended immediate byte69 / r iw IMUL r16, r / m16, imm16 word register ← r / m16 * immediate word69 / r id IMUL r32, r / m32, imm32 doubleword register ← r / m32 * immediate doubleword69 / r iw IMUL r16, imm16 word register ← r / m16 * immediate wordE4 ib IN AL, imm8 Input Byte from IMM8 I / O Port Address INTO ALE5 IB in AX, IMM8 Input Byte from IMM8 I / O Port Address INTO AXE5 IB in Eax, Imm8 Input Byte From IMM8 I / O Port Address Into EAXEC in Al, DX Input Byte from i / O Port in DX INTO ALED IN AX, DX Input Word from I / O Port in DX INTO AXED In Eax, DX Input Doubleword from I / O Port in DX INTO EAXFE / 0 Inc R / M8 Increment R / m Byte by 1F / 0 Inc R / M16 Increment R / M Word by 1FF / 0 Inc R / M32 Increment R / m doubleword by 140 rw INC r16 Increment word register by 140 rd INC r32 Increment doubleword register by 16C INS m8, DX Input byte from I / O port specified in DX into memory location specified in ES: (E) DI6D INS m16, DX Input Word from I / O Port Specified in DX INTO MEMORY
location specified in ES: (E) DI6D INS m32, DX Input doubleword from I / O port specified in DX into memory location specified in ES: (E) DI6C INSB Input byte from I / O port specified in DX into memory location specified with ES: (E) DI6D INSW Input word from I / O port specified in DX into memory location specified in ES: (E) DI6D INSD Input doubleword from I / O port specified in DX into memory location specified in ES: (E) DICC INT 3 Interrupt 3-Trap To Debuggercd Ib Int Imm8 Interrupt Vector Number Specified by Immediate Bytece Into Interrupt 4- IF overflow Flag IS 10F 08 InVD Flush internal caches; initiate flushing of external caches.0F 01/7 INVLPG m Invalidate TLB Entry for page that contains mCF IRET Interrupt return (16-bit operand size) CF IRETD Interrupt return (32-bit operand size) 77 cb JA rel8 Jump Short if Above (CF = 0 and zf = 0) 73 CB Jae Rel8 Jump Short if Above or Equal (CF = 0) 72 CB JB REL8 JUMP SHORT IF BELOW (CF = 1) 76 CB JBE REL8 JUMP SHORT IF BELOW OR Equal (Cf = 1 or zf = 1) 72 CB JC REL8
JUMP SHORT IF Carry (CF = 1) E3 CB JCXZ REL8 JUMP SHORT IF CX Register IS 0E3 CB JECXZ REGOS 074 CB JE REL8 JUMP SHORT IF Equal (zf = 1) 7F CB JG REL8 JUMP SHORT IF GREATER (Zf = 0 and sf = of) 7D CB JGE REL8 JUMP SHORT IF GREATER OR Equal (sf = of) 7C CB JL REL8 JUMP SHORT IF LESS (SF <> of) 7e CB Jle Rel8 Jump Short if Less OR Equal (ZF = 1 or sf <> of) 76 CB JNA REL8 JUMP SHORT IF NOT ABOVE (CF = 1 OR ZF = 1) 72 CB JNAE REL8 JUMP SHORT IF NOT ABOVE OR Equal (cf = 1) 73 CB JNB REL8 JUMP SHORT IF NOT BELOW (CF = 0) 77 CB JNBE REL8 JUMP SHORT IF NOT BELOW OR Equal (CF = 0 and ZF = 0) 73 CB JNC REL8 JUMP SHORT IF NOT Carry (CF = 0) 75 CB JNE REL8 JUMP short if not equal (zf = 0) 7e CB JNG REL8 JUMP SHORT IF NOT GREATER (ZF = 1 or sf <> of) 7C CB JNGE REL8 JUMP SHORT IF NOT GREATER OR Equal (s> of) 7D CB JNL REL8 JUMP SHORT IF CB JNLE REL8 JUMP SHORT IF CB JNLE REL8 JUMP SHORT IF] 71 CB JNO REL8 JUMP SHORT IF NOT OVERFLOW (= 0) 7b CB JNP REL8 JUMP SHORT IF not Parity (PF = 0) 79 CB JNS REL8 JUMP SHORT IF NOT SIGN (sf = 0) 75 CB JNZ REL8
JUMP SHORT IF NOT ZERO (ZF = 0) 70 CB JO REL8 JUMP SHORT IF overflow (= 1) 7A CB JP REL8 JUMP SHORT IF PARITY (PF = 1) 7A CB JPE REL8 JUMP SHORT IF PARITY EVEN (PF = 1) 7b CB JPO REL8 JUMP SHORT IF PARITY ODD (PF = 0) 78 CB JS REL8 JUMP SHORT IF SIGN (sf = 1) 74 CB JZ REL8 JUMP SHORT IF ZERO (ZF = 1) 0F 87 CW / CD JA REL16 / 32 JUMP Near if Above (cf = 0 and zf = 0) 0F 83 CW / CD JAE REL16 / 32 JUMP Near if Above or Equal (CF = 0) 0F 82 CW / CD JB REL16 / 32 JUMP NEAR IF BELOW (CF = 1) 0F 86 CW / CD JBE REL16 / 32 JUMP Near if Below or Equal (cf = 1 or ZF = 1) 0F 82 CW / CD JC REL16 / 32 JUMP NEAR IF Carry (CF = 1) 0F 84 CW / CD JE REL16 / 32 JUMP Near if Equal (zf = 1) 0F 84 CW / CD JZ REL16 / 32 JUMP NEAR IF 0 (ZF = 1) 0f 8F CW / CD JG REL16 / 32 JUMP Near if Greater (zf = 0 and sf = of of) 0F 8D CW / CD JGE REL16 / 32 JUMP Near if Greater OR Equal (sf = of) 0F 8C CW / CD JL REL16 / 32 JUMP NEAR IF LESS (SF <> Of) 0F 8e CW / CD Jle REL16 / 32 JUMP Near if Less or Sf <> of) 0F 86 CW / CD JNA REL16 / 32 JUMP NEAR INA REL ABOVE (CF = 1 or ZF = 1) 0F 82 CW / CD JNAE REL16 / 32 JUMP Near if Not Above or Equal (cf = 1) 0F 83 CW / CD JNB REL16 / 32 JUMP NEAR INB RELOW (CF = 0) 0F 87 CW / CD JNBE REL16 / 32 JUMP Near if not below or equal (cf = 0 and zf = 0) 0F 83 CW / CD JNC REL16 / 32
JUMP Near if not carry (cf = 0) 0F 85 CW / CD JNE REL16 / 32 JUMP NEAR IF NOT Equal (zf = 0) 0F 8E CW / CD JNG REL16 / 32 JUMP NEAR IF NOT GREATER (ZF = 1 OR sf < > Of) 0F 8C CW / CD JNGE REL16 / 32 JNGE REL16 / 32 JUMP NEAR IF NOT GREATER OR Equal (s> of) 0F 8D CW / CD JNL REL16 / 32 JUMP NEAR IF NOT LESS (SF = Of) 0F 8F CW / CD JNLE REL16 / 32 JUMP NEAR IF NOT OR Equal (zf = 0 and sf = of) 0F 81 CW / CD JNO REL16 / 32 JUMP Near if not overflow (= 0) 0F 8B CW / CD JNP REL16 / 32 JUMP NEAR IF NOT PARITY (PF = 0) 0F 89 CW / CD JNS REL16 / 32 JUMP NEAR INS REL16 / 32 JUMP Near if Not Sign (sf = 0) 0F 85 CW / CD JNZ REL16 / 32 JUMP NEAR IF NOT ZERO (ZF = 0) 0F 80 CW / CD JO REL16 / 32 JUMP Near if overflow (= 1) 0F 8A CW / CD JP REL16 / 32 JUMP Near if Parity (PF = 1) 0F 8A CW / CD JPE REL16 / 32 JUMP NEAR IF PARITY EVEN (PF = 1) 0F 8B CW / CD JPO REL16 / 32 JUMP NEAR IF PARITY O DD (PF = 0) 0F 88 CW / CD JS REL16 / 32 JUMP NEAR IF SIGN (SF = 1) 0F 84 CW / CD JZ REL16 / 32 JUMP Near IF 0 (ZF = 1) EB CB JMP Rel8 Jump Short, Relative , displacement relative to next instructionE9 cw JMP rel16 Jump near, relative, displacement relative to next instructionE9 cd JMP rel32 Jump near, relative, displacement relative to next instructionFF / 4 JMP r / m16 Jump near, absolute indirect, add
ress given in r / m16FF / 4 JMP r / m32 Jump near, absolute indirect, address given in r / m32EA cd JMP ptr16: 16 Jump far, absolute, address given in operandEA cp JMP ptr16: 32 Jump far, absolute, address given IN OPERANDFF / 5 JMP M16: 16 JUMP FAR, ABSOLUTE INDIRECT, ADDRESS GIVEN IN M16: 16FF / 5 JMP M16: 32 JUMP FAR, ABSOLUTE INDIRECT, ADDRESS GIVEN IN M16: 329F lahf loading: AH ← EFLAGS (sf: zf: 0 : AF: 0: PF: 1: CF) 0F 02 / R Lar R16, R / M16 R16 ← R / M16 Masked BY FF00H0F 02 / R LAR R32, R / M32 R32 ← R / M32 Masked BY 00FxFF00H0F, AE, / 2 LDMXCSR M32 LOAD MXCSR Register from M32.c5 / R LDS R16, M16: 16 LOAD DS: R16 with Far Pointer from M16 CLDS R32, M16: 32 LOAD DS: R32 with Far Pointer from Memory0F B2 / R LSS R16, M16: 16 LOAD SS: R16 with F Ar Pointer from Memory0F B2 / R LSS R32, M16: 32 LOAD SS: R32 with Far Pointer from M16: 16 LOAD ES: R16 with FAR POINTER FROM MEMORYC4 / R LES R32, M16: 32 LOAD ES: R32 with far Pointer from Memory0F B4 / R LFS R16, M16: 16 LOAD FS: R16 with far Pointer from M16 WITH FAR POINTER FROMORY0F B4 / R LFS R32, M16: 32 LOAD FS: R32 with FAR POINTER FROM MEMORY0F B5 / R LGS R16, M16: 16 Load GS: R16 With Far Pointer from Memory0F B5 / R LGS R32, M16: 32 LOAD GS: R32 with far Pointer from Memory8D / R LEA R16, M Store Effective Address for M in Register R168D / R LEA R32, M Store Effective
address for m in register r32C9 LEAVE SET SP to BP, then pop BPC9 LEAVE SET ESP to EBP, then pop EBP0F AE / 5 LFENCE Serializes load operations.0F 01/2 LGDT m16 & 32 Load m into GDTR0F 01/3 LIDT m16 & 32 Load m into IDTR0F 00/2 LLDT r / m16 Load segment selector r / m16 into LDTR0F 01/6 LMSW r / m16 Loads r / m16 in machine status word of CR0F0 LOCK Asserts LOCK # signal for duration of the accompanying instructionAC LODS m8 Load byte at address DS: (e) Si Into Alad Lods M16 Load Word at Address DS: (E) Si Into Axad Lods M32 Load Doubleword At Address DS: (E) Si Into Eaxac Lodsb Load Byte At Address DS: (E) Si Into Alad LODSW Load word at address DS: (E) SI into AXAD LODSD Load doubleword at address DS: (E) SI into EAXE2 cb LOOP rel8 Decrement count; jump short if count ≠ 0E1 cb LOOPE rel8 Decrement count; jump short if count ≠ 0 and ZF = 1E1 cb LOOPZ rel8 Decrement count; jump short if count ≠ 0 and ZF = 1E0 cb LOOPNE rel8 Decrement count; jump short if count ≠ 0 and ZF = 0E0 cb LOOPNZ rel8 Decrement count; jump short if count ≠ 0 and ZF = 00F 03 / R LSL R16, R / M16 LOAD: R16 ← Segment Limit, Selector R / M160F 03 / R LSL R32, R / M32
Load: r32 ← segment limit, selector r / m320F 00/3 LTR r / m16 Load r / m16 into task register66 0F F7 / r MASKMOVDQU xmm1, xmm2 Selectively write bytes from xmm1 to memory location using the byte mask in xmm2.0F F7 / r MASKMOVQ mm1, mm2 Selectively write bytes from mm1 to memory location using the byte mask in mm2 66 0F 5F / r MAXPD xmm1, xmm2 / m128 Return the maximum double-precision floating-point values between xmm2 / m128 and xmm1. 0F 5F / R MAXPS XMM1, XMM2 / M128 RETURN THE MAXIMUM SINGLE-Precision Floating-Point Values BetWeen XMM2 / M128 and XMM1. F2 0F 5F / R MaxSD XMM1, XMM2 / M64 Return THE MAXIMUM SCALAR DOUBLE-PRECISI on floating-point value between xmm2 / mem64 and xmm1. F3 0F 5F / r MAXSS xmm1, xmm2 / m32 Return the maximum scalar single-precision floating-point value between xmm2 / mem32 and xmm1. 0F AE / 6 MFENCE Serializes load and store Operations.66 0F 5D / R MINPD XMM1, XMM2 / M128 RETURN THE minimum Double-Precision Floating-Point Values BetWeen XMM2 / M128 and XMM1. 0F 5D / R MINPS XMM1, XMM2 / M128 RETURN THE MINIMUM SINGLE-PRECSION FL
Oating-Point Values BetWeen XMM2 / M128 and XMM1. F2 0F 5D / R MINSD XMM1, XMM2 / M64 Return The Minimum Scalar Double-Precision Floating-Point Value BetWeen XMM2 / MEM64 and XMM1. F3 0F 5D / R MINSS XMM1, XMM2 / M32 RETURN THE minimum Scalar Single-Precision Floating-Point Value BetWeen XMM2 / MEM32 and XMM1. 88 / R MOV R / M8, R8 MOVE R / M16, R16 MOVE R16 TO R / M1689 / R MOV R / M32, R32 MOVE R32 TO R / M328A / R MOV R8, R / M8 MOVE R / M8 TO R88B / R MOV R16, R / M16 MOVE R / M16 TO R168B / R MOV R32, R / M32 MOVE R / M32 TO R328C / R MOV R / M16, SREG ** MOVE Segment Register TO R / M168E / R MOV SREG, R / M16 ** MOVE R / M16 TO Segment Registera0 MOV Al, Moffs8 * Move Byte At (seg: offset) To Ala1 MOV AX, MOFFS16 * MOVE WORD AT (seg: offset) To AXA1 MOV EAX, MOFFS32 * MOVE DOUBLORD AT (seg: offset) To Eaxa2 MOV MOFFS8 *, Al Move Al To (Seg: Offset) A3 MOV MOFFS16 *, AX MOVE AX TO (SEG: Offset) A3 MOV MOFFS32 *, EAX MOVE EAX to (seg: offset) B0 RB MOV R8, IMM8 MOVE IMM8 TO R8B8 RW MOV R16, IMM16 MOVE IMM16 TO R16B8 RD MOV R32, IMM32 MOVE IMM32 TO R32C6 / 0 MOV R / M8, IMM8 MOVE IM
M8 TO R / M8C7 / 0 MOV R / M16, IMM16 MOVE IMM16 TO R / M16C7 / 0 MOV R / M32, IMM32 MOVE IM32 TO R / M320F 22 / R MOV CR0, R32 MOVE R32 TO CR00F 22 / R MOV CR2, R32 MOVE R32 TO CR20F 22 / R MOV CR3, R32 MOVE R32 TO CR30F 22 / R MOV CR4, R32 MOVE R32 TO CR40F 20 / R MOV R32, CR0 MOVE CR0 TO R320F 20 / R MOV R32, CR2 MOVE CR2 TO R320F 20 / R MOV R32, CR3 MOVE CR3 TO R320F 20 / R MOV R32, CR4 MOVE CR4 TO R320F 21 / R MOV R32, DR0-DR7 MOVE DEBUG REGISTER TO R320F 23 / R MOV DR0-DR7, R32 MOVE R32 TO Debug Register0f 24 / R MOV R32, TR0-TR7 MOVE TEST REGISTER TO R320F 26 / R MOV TR0-Test Register66 0F 28 / R MOVAPD XMM1, XMM2 / M128 MOVE PACKED DOUBLE-Precision Floating-Point VALUES from xmm2 / m128 to xmm1.66 0F 29 / r MOVAPD xmm2 / m128, xmm1 Move packed double-precision floating-point values from xmm1 to xmm2 / m128. 0F 28 / r MOVAPS xmm1, xmm2 / m128 Move packed single-precision floating -Point Values from XMM2 / M128 TO XMM1.0F 29 / R MOVAPS XMM2 / M128, XMM1 MOVE PACKED SINGLE-PRECISION FLOATING-POINT VALUES WOM XMM1 TO XMM2 / M128. 0F 6E / R MOVD MM, R / M32 Move Doubleword from R / m32 to mm.0f 7e / r MOVD R / M32, MM MOVE DOUBLEWORD FROM MM TO R / M3
2.66 0F 6E / R MOVD XMM, R / M32 Move DoubleWord from R / M32 TO XMM.66 0F 7E / R MOVD R / M32, XMM Move Doubleword from XMM Register TO R / M32.66 0F 6F / R MOVDQA XMM1, XMM2 / m128 Move aligned double quadword from xmm2 / m128 to xmm1.66 0F 7F / r MOVDQA xmm2 / m128, xmm1 Move aligned double quadword from xmm1 to xmm2 / m128.F3 0F 6F / r MOVDQU xmm1, xmm2 / m128 Move unaligned double quadword from xmm2 / m128 to xmm1.F3 0F 7F / r MOVDQU xmm2 / m128, xmm1 Move unaligned double quadword from xmm1 to xmm2 / m128.F2 0F D6 MOVDQ2Q mm, xmm Move low quadword from xmm to mmx register .OF 12 / r MOVHLPS XMM1, XMM2 Move Two Packed Single-Precision Floating-Point Values from High Quadword of XMM2 To Low Quadword Of XMM1. 66 0F 16 / R MOVHPD XMM, M64 MOVE DOUBLE-Precision Floating-Point Value from m64 to high quadword of xmm.66 0F 17 / r MOVHPD m64, xmm Move double-precision floating-point value from high quadword of xmm to m64. 0F 16 / r MOVHPS xmm, m64 Move two packed single-precision floating-point values from m64 to high quadword of xmm.0F 17 / r MOVHPS m64, xmm Move two packed single-precision floating-point values from high quadword of xmm to m64. oF 16 / r MOVLHPS xmm1, xmm2 Move two packed single-precision floating -Point Values
from low quadword of xmm2 to high quadword of xmm1. 66 0F 12 / r MOVLPD xmm, m64 Move double-precision floating-point value from m64 to low quadword of xmm register.66 0F 13 / r MOVLPD m64, xmm Move double-precision floating-point nvalue from low quadword of xmm register to m64. 0F 12 / r MOVLPS xmm, m64 Move two packed single-precision floating-point values from m64 to low quadword of xmm.0F 13 / r MOVLPS m64, xmm Move two packed SINGLE-PRECISION FLOATING-POINT VALUES from Low Quadword of XMM To M64. 66 0F 50 / R MOVMSKPD R32, XMM Extract 2-Bit Sign Mask Of from XMM AND Store in R32.0F 50 / R MOVMSKPS R32, X MM Extract 4-Bit Sign Mask of from XMM and Store in R32.66 0F E7 / R MOVNTDQ M128, XMM MOVE DOUBLE Quadword from XMM to M128 USING NON-TEMPORAL HINT.0F C3 / R MOVNI M32, R32 MOVE DOUBLORD FROM R32 TO m32 using non-temporal hint.66 0F 2B / r MOVNTPD m128, xmm Move packed double-precision floating-point values from xmm to m128 using non-temporal hint. 0F 2B / r mOVNTPS m128, xmm Move packed single-precision floating- Point Values from XMM to M128 U
Sing Non-Temporal Hint. 0F E7 / R MOVNTQ M64, MM MOVE QUADWORD AUMTO M64 USING NON-TEMPORAL HINT.0F 6F / R MOVQ MM, MM / M64 MOVE QUADWORD FROM / M64 TO MM.0F 7F / R MOVQ MM / M64, MM MOVE QUADWORD FROM mm to mm / m64.f3 0f 7e MOVQ XMM1, XMM2 / M64 MOVE QUADWORD FROM XMM2 / MEM64 TO XMM1.66 0F D6 MOVQ XMM2 / M64, XMM1 Move Quadword from XMM1 TO XMM2 / MEM64. F3 0F D6 MOVQ2DQ XMM, MM Move Quadword from mmx to low quadword of XMM.A4 MOVS M8, M8 MOVE BYTE AT AT AT ATDRESS ES: (E) DIA5 MOVS M16, M16 MOVE WORD AT Address DS: (E) Si to Address ES: (E) DIA5 MOVS M32, M32 Move Doubleword At Address DS: (e) Si To Address ES: (E) DIA4 MOVSB MOVE BYTE AT AT AT AT AT ATDRESS DS: (E) Si To Address ES :( E) DIA5 Movsw Move Word At Address DS: (e) Si To Address ES: (E) DI A5 MOVSD MOVE DOUBLORD AT Address DS: (E) Si To Address ES: (E) DIF2 0F 10 / R MOVSD XMM1, XMM2 / M64 MOVE Scalar Double-Precision Floating-Point Value from XMM2 / M64 TO XMM1 Register.f2 0F 11 / R MOVSD XMM2 / M64, XMM Move Scalar Double-Precision Floating-Point Value from XMM1 Register TO XMM2 / M64. F3 0F 10 / R MOVSS XMM1, XMM2 / M32 Move Scalar Single-Precision Floating-Point Value from XMM2 / M64 TO XM
M1 Register.f3 0F 11 / R MOVSS XMM2 / M32, XMM Move Scalar Single-Precision Floating-Point Value from XMM1 Register to XMM2 / M64. 0F BE / R MOVSX R16, R / M8 MOVE BYTE TO WORD WITH SIGN-EXTENSION0F BE / R MOVSX R32, R / M8 MOVE BYTE TO DOUBLEWORD, SIGN-EXTENSION0F BF / R MOVSX R32, R / M16 MOVE WORD TO DOUBLEWORD, SIGN-EXTENSION66 0F 10 / R MOVUPD XMM1, XMM2 / M128 MOVE PACKED DOUBLE-Precision Floating- Point Values from XMM2 / M128 TO XMM1.66 0F 11 / R MOVUPD XMM2 / M128, XMM MOVE PACKED DOUBLE-Precision Floating-Point Values from XMM1 TO XMM2 / M128. 0F 10 / R Movups XMM1, XMM2 / M128 MOVE PACKED SINGLE- Precision Floating-Point Values from XMM2 / M128 to XMM1.0F 11 / R MOVUPS XMM2 / M128, XMM1 MOVE PACKED SINGLE-Precision Floating-Point Values from XMM1 to XMM2 / M128. 0F B6 / R MOVZX R16, R / M8 MOVE BYTE TO WORD WITH ZERO-EXTENSION0F B6 / R MOVZX R32, R / M8 MOVE Byte to DoubleWord, Zero-Extension0F B7 / R MOVZX R32, R / M16 MOVE WORD TO DOUBLORD, ZERO-EXTENSIONF6 / 4 MUL R / M8 Unsigned Multiply (AX ← Al * R / M8) F7 / 4 MUL R / M16 Unsigned Multiply (DX: AX ← AX * R / M16) F7 / 4 MUL R / M32 Unsigned Multiply (EDX: EAX ← EAX * R / M32) 66 0F 59 / R MULPD XMM1, XMM2 / M128 Multiply Packed Double-Precision FLO
Attribute-point values in xm2 / m128 by xmm1. 0F 59 / R MULPS XMM1, XMM2 / M128 MULTIPLY PACKED SINGLE-PRECISION FLOATING-POINT VALUES IN XMM2 / MEM BY XMM1. F2 0F 59 / R Mulsd XMM1, XMM2 / M64 Multiply THE low double-precision floating-point value in xmm2 / mem64 by low double-precision floating-point value in xmm1. F3 0F 59 / r MULSS xmm1, xmm2 / m32 Multiply the low single-precision floating-point value in xmm2 / mem by The Low Single-Precision Floating-Point Value in XMM1. F6 / 3 NEG R / M8 Two's Complement Negate R / M8F 7/3 NEG R / M16 Two's Complement Negate R / M16F7 / 3 NEG R / M32 Two's Complement Negate R / M3290 NOP No Operationf6 / 2 Not R / M8 Reverse Each Bit of R / M8F7 / 2 Not R / M16 Reverse Each Bit OF R / M16F7 / 2 NOT R / M32 Reverse Each Bit of R / M320C IB OR Al, IMM8 Al or Imm80d IW OR AX, IMM16 AX OR IMM160D ID OR EAX, IMM32 EAX OR IMM3280 / 1 Ib OR R / M8, IMM8 R / M8 OR IMM881 / 1 IW OR R / M16, IMM16 R / M16 OR IMM1681 / 1 ID OR R / M32, IMM32 R / M32 OR IMM3283 / 1
IB OR R / M16, IMM8 R / M16 OR IMM8 (Sign-Extended) 83/1 Ib OR R / M32, IMM8 R / M32 OR IMM8 (SIGN-EXTENDED 08 / R OR R / M8, R8 R / M8 OR R809 / R OR R / M16, R16 R / M16 OR R1609 / R OR R / M32, R32 R / M32 OR R320A / R OR R8, R / M8 R8 OR R / M80B / R OR R16, R / M16 R16 OR R / M160B / R OR R32, R / M32 R32 OR R / M3266 0F 56 / R ORPD XMM1, XMM2 / M128 Bitwise or OR OR OF XMM2 / M128 AND XMM1.0F 56 / R ORPS XMM1, XMM2 / M128 Bitwise OR of XMM2 / M128 and XMM1E6 IB OUT IMM8, Al Output Byte IN Al To I / O Port Address IMM8E7 IB OUT IMM8, AX OUTPUT WORD IN AX To I / O Port Address IMM8E7 IB OUT IMM8, EAX Output Doubleword in Eax To I / O Port Address Imm8ee Out DX, Al Output Byte In DXEF OUT DX, AX Output Word In DXEF OUT DX, EAX OUTPUT DOUBLORD IN DX6E OUTS DX, M8 OUTPUT BYTE from M8 Output Byte From Memory Location Specified in DS: (E) Si To I / O Port specified in DX6F OUTS DX, m16 Output word from memory location specified in DS: (E) SI to I / O port specified in DX6F OUTS DX, m32 Output doubleword from memory location specified in DS: (E) SI to I / O port Specified in DX6E Outsb Output Byte from Memory Location Specified
in DS: (E) SI to I / O port specified in DX6F OUTSW Output word from memory location specified in DS: (E) SI to I / O port specified in DX6F OUTSD Output doubleword from memory location specified in DS: (E) SI to I / O port specified in DX 0F 63 / r PACKSSWB mm1, mm2 / m64 Converts 4 packed signed word integers from mm1 and from mm2 / m64 into 8 packed signed byte integers in mm1 using signed saturation.66 0F 63 / r PACKSSWB XMM1, XMM2 / M128 Converts 8 Packed Signed Word Integers from xmm1 and from xxm2 / m128 INTO 16 PACKED SIGNED BYTE INTEGERS in XXM1 Using Signed Saturation.0F 6B / R PackssDW MM1, MM2 / M64 Converts 2 packed signed doubleword integers from mm1 and from mm2 / m64 into 4 packed signed word integers in mm1 using signed saturation.66 0F 6B / r PACKSSDW xmm1, xmm2 / m128 Converts 4 packed signed doubleword integers from xmm1 and from xxm2 / m128 into 8 packed Signed Word Integers in XXM1 Using Signed Saturation. 0f 67 / R PackusWB mm, MM / M64 Converts 4 Signed Word Integers from MM and 4 Signed Word Integers from MM / M64 INTO 8 Unsigned
byte integers in mm using unsigned saturation.66 0F 67 / r PACKUSWB xmm1, xmm2 / m128 Converts 8 signed word integers from xmm1 and 8 signed word integers from xmm2 m128 into 16 unsigned byte integers in xmm1 using unsigned saturation /. 0F FC / r Paddb mm, mm / mm / mm / mm / mm / mm / mm / mm / mm / m64 and mm.66 0F FC / R PADDB XMM1, XMM2 / M128 Add Packed Byte Integers from XMM2 / M128 and XMM1.0F FD / R Paddw MM, MM / M64 Add Packed Word Integers from MM / M64 and MM.66 0F FD / R PPDW XMM1, XMM2 / M128 Add Packed Word Integers from XMM2 / M128 and XM1.0F Fe / R Paddd MM, MM / M64 Add Packed Doubleword Integers from MM / M64 And mm.66 0f Fe / R Paddd XMM1, XMM2 / M128 Add Packed Doubleword Integers from XMM2 / M128 and XMM1.0F D4 / R Paddq MM1, MM2 / M64 Add quadword integer mm2 / m64 to mm166 0F D4 / r PADDQ xmm1, xmm2 / m128 Add packed quadword integers xmm2 / m128 to xmm10F EC / r PADDSB mm, mm / m64 Add packed signed byte integers from mm / m64 and mm and saturate the results.66 0F EC / r PADDSB xmm1, xmm2 / m128 Add packed signed byte integers from xmm2 / m128 and xmm1 saturate the results.0F ED / r PADDSW mm, mm / m64 Add packed signed word integers from mm / m64 and mm and Saturate The Results.66 0F ED / R PADDSW XMM1, XMM2 / M128 Add Packed Signed Word Integers from XM2 / M128
and xmm1 and saturate the results. 0F DC / r PADDUSB mm, mm / m64 Add packed unsigned byte integers from mm / m64 and mm and saturate the results.66 0F DC / r PADDUSB xmm1, xmm2 / m128 Add packed unsigned byte integers from xmm2 / m128 and xmm1 saturate the results.0F DD / r PADDUSW mm, mm / m64 Add packed unsigned word integers from mm / m64 and mm and saturate the results.66 0F DD / r PADDUSW xmm1, xmm2 / m128 Add packed unsigned word Integers from XMM2 / M128 TO XMM1 and Saturate The Results. 0F DB / R PAND MM, MM / M64 Bitwise and MM / M64 and MM.66 0F DB / R PAND XMM1, XMM2 / M128 Bitwise And Of XMM2 / M128 and XMM1. 0F DF / R PANDN MM, MM / M64 Bitwise and Not Of OF MM / M64 and MM.66 0F DF / R PANDN XMM1, XMM2 / M128 Bitwise and Not of XM2 / M128 and XMM1.F3 90 PAUSE GIVES HINT TO Processor That Improves Performance of Spin-Wait Loops.0F E0 / R PAVGB MM1, MM2 / M64 Average packed unsigned byte integers from mm2 / m64 and mm1 with rounding.66 0F E0, / r PAVGB xmm1, xmm2 / m128 Average packed unsigned byte integers from xmm2 / m128 and xmm1 with rounding.0F E3 / r PAVGW mm1, mm2 / m64 Average Packed unsigned Word Integers from mm2 / m64 and mm1 with runk.66 0f E3 / r
PAVGW xmm1, xmm2 / m128 Average packed unsigned word integers from xmm2 / m128 and xmm1 with rounding. 0F 74 / r PCMPEQB mm, mm / m64 Compare packed bytes in mm / m64 and mm for equality.66 0F 74 / r PCMPEQB xmm1, XMM2 / M128 compare packed bytes in xmm2 / m128 and xmm1 for equality.0f 75 / r pcmpeqw mm, mm / m64 compare pcmpeqw xmm1, xmm2 / m128 compare packed words in xmm2 / m128 and xmm1 for equality.0F 76 / r PCMPEQD mm, mm / m64 Compare packed doublewords in mm / m64 and mm for equality.66 0F 76 / r PCMPEQD xmm1, xmm2 / m128 Compare packed doublewords in xmm2 / m128 And xmm1 for equality.0f 64 / r PCMPGTB MM, MM / M64 Compa e packed signed byte integers in mm and mm / m64 for greater than.66 0F 64 / r PCMPGTB xmm1, xmm2 / m128 Compare packed signed byte integers in xmm1 and xmm2 / m128 for greater than.0F 65 / r PCMPGTW mm, mm / m64 Compare packed signed word integers in mm and mm / m64 for greater than.66 0F 65 / r PCMPGTW xmm1, xmm2 / m128 Compare packed signed word integers in xmm1 and xmm2 / m128 for greater than.0F 66 / r PCMPGTD mm, mm / m64 compare packed sign doubleword integers in mm and mm / m64 fornow greater tour.6
6 0F 66 / r PCMPGTD xmm1, xmm2 / m128 Compare packed signed doubleword integers in xmm1 and xmm2 / m128 for greater than. 0F C5 / r ib PEXTRW r32, mm, imm8 Extract the word specified by imm8 from mm and move it to r32 .66 0F C5 / R IB PEXTRW R32, XMM INTO mm at the word position specified by imm866 0f c4 / r ib Pinsrw xmm, r32 / m16, imm8 move the low word of r32 or from m16 INTO XMM at the word position specified by imm8. 0f f5 / r pmaddwd mm, mm / M64 MULTIPLY THE PACKED Words in mm by the packed wo rds in mm / m64, add adjacent doubleword results, and store in mm.66 0F F5 / r PMADDWD xmm1, xmm2 / m128 Multiply the packed word integers in xmm1 by the packed word integers in xmm2 / m128, add adjacent doubleword results, and store in xmm1. 0F EE / r PMAXSW mm1, mm2 / m64 Compare signed word integers in mm2 / m64 and mm1 and return maximum values.66 0F EE / r PMAXSW xmm1, xmm2 / m128 Compare signed word integers in xmm2 / m128 and x
mm1 and return maximum values. 0F DE / r PMAXUB mm1, mm2 / m64 Compare unsigned byte integers in mm2 / m64 and mm1 and returns maximum values.66 0F DE / r PMAXUB xmm1, xmm2 / m128 Compare unsigned byte integers in xmm2 / m128 and xmm1 and returns maximum values. 0F EA / r PMINSW mm1, mm2 / m64 Compare signed word integers in mm2 / m64 and mm1 and return minimum values.66 0F EA / r PMINSW xmm1, xmm2 / m128 Compare signed word integers in xmm2 / MINIMUM VALUES. 0F DA / R PMINUB MM1, MM2 / M64 COMPARE UNSIGNED BYTE INTEGERS IN MM2 / M64 and MM1 And Returns minimum Values.66 0F DA / R PMINUB xmm1, xmm2 / m128 Compare unsigned byte integers in xmm2 m128 and xmm1 and returns minimum values /. 0F D7 / r PMOVMSKB r32, mm Move a byte mask of mm to r32.66 0F D7 / r PMOVMSKB r32, xmm Move a byte mask of xmm to r32.0F E4 / r PMULHUW mm1, mm2 / m64 Multiply the packed unsigned word integers in mm1 register and mm2 / m64, and store the high 16 bits of the results in mm1.66 0F E4 / r PMULHUW xmm1, xmm2 / M128 MULTIPLY THE PACKED UNSIGNED WORD INTEGERS in XMM1 And Store THE HI
GH 16 bits of the results in xmm1. 0f E5 / R PMULHW MM, MM / M64 MULTIPLY THE PACKED SIGNED Word Integers in mm1 register and mm2 / mm2 / mm2 / mm2 / mm2 / mm2 / mm2 / mm2/th 16 bits of the results in mm1.66 0f E5 / R PMULHW xmm1, xmm2 / m128 Multiply the packed signed word integers in xmm1 and xmm2 / m128, and store the high 16 bits of the results in xmm1. 0F D5 / r PMULLW mm, mm / m64 Multiply the packed signed word integers in mm1 register And mm2 / mm2 / mm2 / mm2 / mm2 / mm1.66 0f d5 / r pmullw xmm1, xmm2 / m128 multiply the Packed SIGNED WORDERS in xmm1 and xmm2 / m128, and store the low 16 bits of the results in xmm1. 0F F4 / r PMULUDQ mm1, mm2 / m64 Multiply unsigned doubleword integer in mm1 by unsigned doubleword integer in mm2 / m64, and store the quadword result in MM1.66 of F4 / R Pmuludq XMM1, XMM2 / M128 MULTIPLY PACKED UNSIGNED DOUBLEWORD INTEGERS in XMM1 by Packed Unsigned Doubleword Integers in XMM2 / M128, And Store The Quadword Results In XMM1.
8F / 0 POP r / m16 Pop top of stack into m16; increment stack pointer8F / 0 POP r / m32 Pop top of stack into m32; increment stack pointer58 rw POP r16 Pop top of stack into r16; increment stack pointer58 rd POP r32 Pop top of stack into r32; increment stack pointer1F POP DS Pop top of stack into DS; increment stack pointer07 POP ES Pop top of stack into ES; increment stack pointer17 POP SS Pop Pop pop of stack into SS; increment stack pointer0F A1 POP FS Pop Top of Stack Into Fs; Increment Stack Pointer0f A9 Pop Gs Pop Top of Stack Into Gs; Increment Stack Pointer61 Pop Di, Si, BP, BX, DX, CX, And AX61 Pop Adi, ESI, EBP, EBX, EDX, ECX, And Eax9d POPF POP TOP OF Stack INTO LOWER 16 BITS OF EFLAGS9D POPFD POP TOP OF Stack INTO EFLAGS0F EB / R POR MM, MM / M64 Bitwise OR OF MM / M64 and MM.66 0F EB / R POR XMM1, XMM2 / M128 Bitwise OR OF XMM2 / M128 and XMM1.0F 18/1 Prefetcht0 M8 Move Data from M8 Closer To the processor Using T0 HINT.0F 18/2 Prefetcht1 M8 MOVE DATA from M8 Closer To The Processor USING T1 HINT.0F 18/3 Prefetcht2 M8 Move Data From m8 closer to the processor using t2 hint.0f
18/0 PREFETCHNTA m8 Move data from m8 closer to the processor using NTA hint.0F F6 / r PSADBW mm1, mm2 / m64 Computes the absolute differences of the packed unsigned byte integers from mm2 / m64 and mm1; differences are then summed to produce an unsigned word integer result.66 0F F6 / r PSADBW xmm1, xmm2 / m128 Computes the absolute differences of the packed unsigned byte integers from xmm2 / m128 and xmm1; the 8 low differences and 8 high differences are then summed separately to produce two unsigned Word Integer Results. 66 0F 70 / R IB PSHUFD XMM1, XM m2 / m128, imm8 Shuffle the doublewords in xmm2 / m128 based on the encoding in imm8 and store the result in xmm1. F3 0F 70 / r ib PSHUFHW xmm1, xmm2 / m128, imm8 Shuffle the high words in xmm2 / m128 based on the Encoding in imm8 and store the result in xmm1. f2 0f 70 / r ib pshuflw xmm1, xmm2 / m128, imm8 shuffle the Low Words in xmm2 / m128 based on the encoding in imm8 and store the result
IN XMM1. 0F 70 / R IB PSHUFW MM1, MM2 / M64, IMM8 SHUFFLE THE WORDS IN MM2 / M64 BASEDOT INCODING IN IMM8 and Store THE ENCODING IN IMM8 and Store THE RESUNCODING IN IMM8 and Store THE RESUNCODING IN MM1. 66 0F 73/7 IB PSLLDQ XMM1, IMM8 Shift XMM1 LEFT BY IMM8 bytes while shifting in 0s.0f f1 / r psllw mm, mm / mm / mm / mm / mm / mm / mm / mm / mm / mm / m64 while shifting in 0s.66 0F f1 / r psllw xmm1, xmm2 / m128 shift Words in xmm1 left by xmm2 / M128 While Shifting In 0S.0F 71/6 IB PSLLW MM, Imm8 Shift Words in mm Left by imm8 while shifting in 0s.66 0f 71/6 ib psllw xmm1, imm8 shift words in xmm1 left by imm8 while shifting in 0s.0f F2 / R pslld mm, mm / mm / mm left by mm / m64 while shifting in 0s.66 0F F2 / r PSLLD xmm1, xmm2 / m128 Shift doublewords in xmm1 left by xmm2 / m128 while shifting in 0s.0F 72/6 ib PSLLD mm, imm8 SHift doublewords in mm left by imm8 while shifting in 0s .66 0F 72/6 IB PSLLD XMM1, IMM8 Shift Doublewords in Xmm1 Left by Imm8 While Shifting In 0S.0F F3 / R PSLLQ MM, MM / M64 Shift Quadword In mm Left by mm / m64 while shifting in 0s.66 0f f3 / R psllq xmm1, xmm2 / m128 shift quadwords in xmm1 left by xmm2 / m12
8 while shifting in 0s.0F 73/6 ib PSLLQ mm, imm8 SHift quadword in mm left by imm8 while shifting in 0s.66 0F 73/6 ib PSLLQ xmm1, imm8 SHift quadwords in xmm1 left by imm8 while shifting in 0s.0F E1 / R psraw mm, mm / mm / mm / mm / mm / mm / mm / mm / mm / mm / mm / mm / m12. Xmm2 / m128 shift Words in xmm1 right by xmm2 / m128 while shifting in sign. 0F 71/4 ib PSRAW mm, imm8 SHift words in mm right by imm8 w hile shifting in sign bits66 0F 71/4 ib PSRAW xmm1, imm8 SHift words in xmm1 right by imm8 while shifting in sign bits0F E2 / r PSRAD mm, mm / M64 Shift Doublew Ords in mm Right BY mm / m64 while shifting in sign bits.66 0f E2 / r PSRAD XMM1, XMM2 / M128 Shift DoubleWord in Xmm1 Right BY XMM2 / M128 While Shifting In Sign Bits.0F 72/4 IB PSRAD MM, IMM8 Shift doublewords in mm right by imm8 while shifting in sign bits.66 0F 72/4 ib PSRAD xmm1, imm8 SHift doublewords in xmm1 right by imm8 while shifting in sign bits.66 0F 73/3 ib PSRLDQ xmm1, imm8 SHift xmm1 right by imm8 While Shifting In 0S.0F D1 / R PSRLW MM, MM / M64 Shift Words in MM Right by Amount Specified in
mm / m64 while shifting in 0s.66 0F D1 / r PSRLW xmm1, xmm2 / m128 Shift words in xmm1 right by amount specified in xmm2 / m128 while shifting in 0s.0F 71/2 ib PSRLW mm, imm8 SHift words in mm right by imm8 while shifting in 0s.66 0F 71/2 ib PSRLW xmm1, imm8 SHift words in xmm1 right by imm8 while shifting in 0s.0F D2 / r PSRLD mm, mm / m64 SHift doublewords in mm right by amount specified in mm / m64 while shifting in 0s.66 0F D2 / r PSRLD xmm1, xmm2 / m128 Shift doublewords in xmm1 right by amount specified in xmm2 / m128 while shifting in 0s.0F 72/2 ib PSRLD mm, imm8 SHift doublewords in mm right by imm8 While Shifting In 0S.66 0F 72/2 IB Psrld XMM1, IMM8 Shift Doublewords in Xmm1 Right By imm8 while shifting in 0s.0F D3 / r PSRLQ mm, mm / m64 SHift mm right by amount specified in mm / m64 while shifting in 0s.66 0F D3 / r PSRLQ xmm1, xmm2 / m128 Shift quadwords in xmm1 right by amount specified in xmm2 / m128 while shifting in 0s.0F 73/2 ib PSRLQ mm, imm8 SHift mm right by imm8 while shifting in 0s.66 0F 73/2 ib PSRLQ xmm1, imm8 SHift quadwords in xmm1 right by imm8 while shifting in 0s. 0F F8 / R PSUBB MM, MM / M64 S Subtract Packed Byte Integers In MM / M64 from Packe
d byte integers in mm.66 0F F8 / r PSUBB xmm1, xmm2 / m128 Subtract packed byte integers in xmm2 / m128 from packed byte integers in xmm1.0F F9 / r PSUBW mm, mm / m64 Subtract packed word integers in mm / m64 from packed word integers in mm.66 0F F9 / r PSUBW xmm1, xmm2 / m128 Subtract packed word integers in xmm2 / m128 from packed word integers in xmm1.0F FA / r PSUBD mm, mm / m64 Subtract packed doubleword integers in mm / m64 from packed doubleword integers in mm.66 0F FA / r PSUBD xmm1, xmm2 / m128 Subtract packed doubleword integers in xmm2 / mem128 from packed doubleword integers in xmm1. 0F FB / r PSUBQ mm1, mm2 / m64 Subtract quadword inte ger in mm1 from mm2 /m64.66 0F FB / r PSUBQ xmm1, xmm2 / m128 Subtract packed quadword integers in xmm1 from xmm2 /m128.0F E8 / r PSUBSB mm, mm / m64 Subtract signed packed bytes in mm / m64 from signed packed bytes in mm and saturate results.66 0F E8 / r PSUBSB xmm1, xmm2 / m128 Subtract packed signed byte integers in xmm2 m128 from packed signed byte integers / in xmm1 and saturate results.0F E9 / r PSUBSW mm, mm / m64 Subtract Signed Packed Words in mm / mm and satura
te results.66 0F E9 / r PSUBSW xmm1, xmm2 / m128 Subtract packed signed word integers in xmm2 m128 from packed signed word integers / in xmm1 and saturate results. 0F D8 / r PSUBUSB mm, mm / m64 Subtract unsigned packed bytes in mm / m64 from unsigned packed bytes in mm and saturate result.66 0F D8 / r PSUBUSB xmm1, xmm2 / m128 Subtract packed unsigned byte integers in xmm2 / m128 from packed unsigned byte integers in xmm1 and saturate result.0F D9 / r PSUBUSW mm, MM / M64 Subtract UNSIGNED PACKED WORDS IN MM / M64 from Unsigned Packed Words in MM And Sature Result.66 0F D9 / R PSUBUSW XMM1, XMM2 / M128 Subtract Packed Unsigned Word Integers in XM2 / M128 from packed unsigned word integers in xmm1 and saturate result. 0F 68 / r PUNPCKHBW mm, mm / m64 Unpack and interleave high-order bytes from mm and mm / m64 into mm.66 0F 68 / r PUNPCKHBW xmm1, xmm2 / m128 Unpack and interleave high-order bytes from xmm1 and xmm2 / m128 into xmm1.0F 69 / r PUNPCKHWD mm, mm / m64 Unpack and interleave high-order words from mm and mm / m64 into mm.66 0F 69 / r PUNPCKHWD xmm1, xmm2 / M128 Unpack and Interleave High-Order Words from
xmm1 and xmm2 / m128 into xmm1.0F 6A / r PUNPCKHDQ mm, mm / m64 Unpack and interleave high-order doublewords from mm and mm / m64 into mm.66 0F 6A / r PUNPCKHDQ xmm1, xmm2 / m128 Unpack and interleave high- order doublewords from xmm1 and xmm2 / m128 into xmm1.66 0F 6D / r PUNPCKHQDQ xmm1, xmm2 / m128 Unpack and interleave high-order quadwords from xmm1 and xmm2 / m128 into xmm1 0F 60 / r PUNPCKLBW mm, mm / m32 interleave low- ORDER BYTES from MM and MM / M32 INTO MM.66 0F 60 / R PUNPCKLBW XMM1, XMM2 / M128 Interleave Low-Order Bytes from XMM1 and XMM2 / M128 INTO XMM1.0F 61 / R PUNPCKLWD MM, MM / M32 Interleave Low-ORDER Words from mm and mm / M32 INTO MM.66 0F 61 / R PUNPCKLWD XMM1, XMM2 / M128 Interleave Low-Order Words from XMM1 and XMM2 / M128 INTO XMM1.0F 62 / R PUNPCKLDQ MM, MM / M32 Interleave Low-Order Doublewords from MM and MM / m32 into mm.66 0F 62 / r PUNPCKLDQ xmm1, xmm2 / m128 Interleave low-order doublewords from xmm1 and xmm2 / m128 into xmm1.66 0F 6C / r PUNPCKLQDQ xmm1, xmm2 / m128 Interleave low-order quadwords from xmm1 and xmm2 / M128 INTO XMM1 Register FF / 6 PUSH
r / m16 Push r / m16FF / 6 PUSH r / m32 Push r / m3250 rw PUSH r16 Push r1650 rd PUSH r32 Push r326A PUSH imm8 Push imm868 PUSH imm16 Push imm1668 PUSH imm32 Push imm320E PUSH CS Push CS16 PUSH SS Push SS1E PUSH DS Push DS06 Push ES Push ES0F A0 Push FS Push FS0F A8 Push GS Push GS60 Pusha Push AX, CX, DX, BX, Original SP, BP, SI, AND DI60 PUSHAD PUSH EAX, ECX, EDX, EBX, Original ESP, EBP , ESI, AND EDI9C Pushf Push Lower 16 Bits of Eflags9c Pushfd Push EFLAG S0F EF / R PXOR MM, MM / M64 Bitwise XOR OF MM / M64 and MM.66 0F EF / R PXOR XMM1, XMM2 / M128 Bitwise XOR OF XM2 / M128 and XMM1.D0 / 2 RCL R / M8, 1 Rotate 9 BITS (CF, R / M8) Left Onced2 / 2 RCL R / M8, CL ROTATE 9 BITS (CF, R / M8) Left CL Timesc0 / 2 Ib RCl R / M8, IMM8 Rotate 9 BITS (CF, R / M8) Left Imm8 Timesd1 / 2 RCL R / M16, 1 Rotate 17 BITS (CF, R / M16) Left Onced3 / 2 RCl R / M16, CL ROTATE 17 BITS (CF, R / M16) Left Cl Timesc1 / 2 IB RCL R / M16, IMM8 Rotate 17 BITS (CF, R / M16) Left imm8 Timesd1 / 2 RCL R / M32, 1 Rotate 33 BITS (CF, R / M32) Left Onced3 / 2 RCL R /
M32, Cl Rotate 33 BITS (CF, R / M32) Left Cl Timesc1 / 2 Ib RTCL R / M32, I MM8 Rotate 33 BITS (CF, R / M32) LEFT IMM8 TIMESD0 / 3 RCR R / M8, 1 Rotate 9 BITS (CF, R / M8) Right Onced2 / 3 RCR R / M8, CL ROTATE 9 BITS (CF, R / M8) Right Cl Timesc0 / 3 Ib RCR R / M8, IMM8 Rotate 9 BITS (CF, R / M8) Right IMM8 TIMESD1 / 3 RTR R / M16, 1 Rotate 17 BITS (CF, R / M16) Right Onced3 / 3 RCR R / M16, CL ROTATE 17 BITS (CF, R / M16) Right Cl Timesc1 / 3 Ib RCR R / M16 , IMM8 Rotate 17 Bits (CF, R / M16) Right IMM8 TIMESD1 / 3 R / M32, 1 Rotate 33 BITS (CF, R / M32) Right Onced3 / 3 RCR R / M32, CL Rotate 33 BITS (CF, R / m32) Right Cl Timesc1 / 3 Ib Rotate 33 BITS (CF, R / M32) RIGHT IMM8 TIMESD0 / 0 ROL R / M8, 1 ROTATE 8 BITS R / M8 LEFT ONCED2 / 0 ROL R / M8 , CL ROTATE 8 BITS R / M8 IB ROL R / M8, IMM8 Rotate 8 BITS R / M8 LEFT IMM8 TIMESD1 / 0 ROL R / M16, 1 ROTATE 16 BITS R / M16 LEFT ONCED3 / 0 ROL R / M16, Cl Rotate 16 BITS R / M16 Left Cl Timesc1 / 0 Ib ROL R / M16, IMM8 ROTATE 16 BITS R / M16 LEFT IMM8 TIMESD1 / 0 ROL R / M32, 1 Rotate 32 BITS R / M32 LEFT ONCED3 / 0 ROL R / M32 , CL ROTATE 32 BITS R / M32 Left Cl Timesc1 / 0 Ib ROL R / M32, IMM8 ROTATE 32 BITS R / M32 LEFT IMM8 TIMESD0 / 1 ROR R / M8, 1 ROTATE 8 BITS R / M8 Right Onced2 / 1 R / M8, CL Rotate 8 BITS R / M8 Right Cl Timesc0 / 1 Ib R / M8, IMM8
ROTATE 8 BITS R / M16 RIGHT IMM8 TIMESD1 / 1 ROUR R / M16, 1 Rotate 16 BITS R / M16 Right Onced3 / 1 R / M16, CL ROTATE 16 BITS R / M16 RIGHT CL TIMESC1 / 1 IB ROR R / M16, IMM8 Rotate 16 BITS R / M16 RIGHT IMM8 TIMESD1 / 1 ROR R / M32, 1 ROTATE 32 BITS R / M32 Right Onced3 / 1 R / M32, CL Rotate 32 BITS R / M32 RIGHT CL TIMESC1 / 1 Ib R / M32 , imm8 Rotate 32 bits r / m32 right imm8 times0F 53 / r RCPPS xmm1, xmm2 / m128 Computes the approximate reciprocals of the packed single-precision floating-point values in xmm2 / m128 and stores the results in xmm1. F3 0F 53 / r RCPSS XMM1, XMM2 / M32 computes the approximate reciprocal of the scalar single-precision floating-point value in xmm2 / m32 and stores the result in xmm1 0F 32 RDMSR Load MSR specified by ECX into EDX:. EAX0F 33 RDPMC Read performance-monitoring counter specified by ECX into EDX: EAX0F 31 RDTSC Read time-stamp counter into EDX: EAXF3 6C REP INS r / m8 , DX INPUT (E) CX bytes from Port DX INTO ES: [E) DI] F3 6D Rep INS R / M16, DX INPUT (E) CX Words from Port DX INTO ES: [(E) DI] F3 6D Rep INS R / M32, DX INPUT (E) CX Doublewords from Port DX INTO ES: [(E) DI] F3 A4 Rep MOVS M8, M8 MOVE
(E) cx bytes from DS: [(e) Si] to es: [e) DI] F3 A5 REP MOVS M16, M16 MOVE (E) CX Words from DS: [(E) Si] to ES: [( E) di] f3 A5 Rep MOVS M32, M32 MOVE (E) CX Doublewords from DS: [(E) Si] To ES: [(E) DI] F3 6E Rep OUTS DX, R / M8 OUTPUT (E) CX BYtes From DS: [(e) Si] To Port DXF3 6F Rep OUTS DX, R / M16 OUTPUT (E) CX Words from DS: [(E) Si] To Port DXF3 6F Rep OUTS DX, R / M32 OUTPUT (E) Cx Doublewords from DS: [(E) Si] To Port DXF3 AC REP LODS Al Load (e) cx bytes from DS: [(E) Si] To Alf3 Ad Rep LODS AX LOAD (E) CX Words from DS: [( E) Si] TO AXF3 AD REP LODS EAX LOAD (E) CX Doublewords from DS: [(E) Si] To Eaxf3 AA Rep Stos M8 Fill (e) CX BYTES AT ES: [(E) DI] with Alf3 AB Rep STOS M16 FILL (E) CX Words At ES: [(E) DI] WITH AXF3 AB REP Stos M32 Fill (e) CX Doublewords At ES: [(E) DI] with Eaxf3 A6 REPE CMPS M8, M8 FIND NONMATCHING BYTES IN ES: [(E) Si] F3 A7 REPE CMPS M16, M16 Find Nonmatch Words in ES: [(E) DI] and DS: [( E) Si] F3 A7 REPE CMPS M32, M32 Find Nonmatching Doublewords in ES: [(E) DI] and DS: [(e) Si] F3 AE Repe SCAS M8 Find Non-Al byte Starting At ES: [(E) Di] F3 AX Word Starting At ES: [(E) DI] F3 AF Repe Scas M32 Find Non DoubleWord Starting At ES: [(E) DI] F2 A6 Repne Cmps M8, M8 Find Matching Bytes in ES: [(E) DI] and DS: [(e) Si] F2 A7 RepNE CMPS M16, M16 Find Matching Words in ES: [(E) DI] and DS: [(e) Si] F2 A7 Repne CMPS M3
2, M32 Find Matching Doublewords in ES: [(E) DI] and DS: [(e) Si] F2 AE RepNE SCAS M8 FIND AL, Starting At ES: [(E) DI] F2 AF RepNE SCAS M16 FIND AX, starting at ES: [(E) DI] F2 AF REPNE SCAS m32 Find EAX, starting at ES: [(E) DI] C3 RET Near return to calling procedurecb RET Far return to calling procedureC2 iw RET imm16 Near return to calling procedure and pop imm16 bytes from stackCA iw RET imm16 Far return to calling procedure and pop imm16 bytes from stack0F AA RSM Resume operation of interrupted program0F 52 / r RSQRTPS xmm1, xmm2 / m128 Computes the approximate reciprocals of the square roots of the packed single-precision floating -p oint values in xmm2 / m128 and stores the results in xmm1. F3 0F 52 / r RSQRTSS xmm1, xmm2 / m32 Computes the approximate reciprocal of the square root of the low single-precision floating-point value in xmm2 / m32 and stores the results In Xmm1. 9e Sahf Loads sf, ZF, AF, PF, AND CF from Ah INTO EFLAGS RegisterD0 / 4 SAL R / M8, 1 Multiply R / M8 by 2, Onced2 / 4 Sal R / M8, CL Multiply R / M8 by 2, CL TIMESC0 / 4
IB Sal R / M8, IMM8 MULTIPLY R / M8 BY 2, IMM8 TIMESD1 / 4 SAL R / M16, 1 MULTIPLY R / M16 BY 2, ONCED3 / 4 SAL R / M16, CL Multiply R / M16 BY 2, CL Timesc1 / 4 Ib Sal R / M16, IMM8 MULTIPLY R / M16 BY 2, IMM8 TIMESD1 / 4 SAL R / M32, 1 Multiply R / M32 by 2, ONCED3 / 4 SAL R / M32, CL Multiply R / M32 BY 2, CL TIMESC1 / 4 IB SAL R / M32, IMM8 MULTIPLY R / M32 BY 2, IMM8 TIMESD0 / 7 SAR R / M8, 1 SIGNED DIVIDE * R / M8 BY 2, ONCED2 / 7 SAR R / M8, CL Signed Divide * R / M8 BY 2, CL TIMESC0 / 7 IB SAR R / M8, IMM8 Signed Divide * R / M8 BY 2, IMM8 TIMESD1 / 7 SAR R / M16, 1 SIGNED DIVIDE * R / M16 BY 2, ONCED3 / 7 SAR R / M16, CL Signed Divide * R / M16 by 2, Cl Timesc1 / 7 Ib Sar R / M16, IMM8 Signed Divide * R / M16 BY 2, IMM8 TIMESD1 / 7 SAR R / M32, 1 S IGNED DIVIDE * R / M32 BY 2, ONCED3 / 7 SAR R / M32, CL Signed Divide * R / M32 by 2, CL Timesc1 / 7 Ib Sar R / M32, IMM8 Signed Divide * R / M32 by 2, IMM8 TIMESD0 / 4 SHL R / M8, 1 MULTIPLY R / M8 BY 2, ONCED2 / 4 SHL R / M8, CL MULTIPLY R / M8 BY 2, CL TIMESC0 / 4 IB SHL R / M8, IMM8 Multiply R / M8 BY 2, IMM8 TIMESD1 / 4 SHL R / M16, 1 MULTIPLY R / M16 by 2, ONCED3 / 4 SHL R / M16, CL MULTIPLY R / M16 by 2, Cl Timesc1 / 4 Ib SHL R / M16, IMM8 Multiply R / M16 by 2, IMM8 TIMESD1 / 4 SHL R / M32, 1 MULTIPLY R / M32 by 2, OnCed3 / 4 SHL R / M32, CL Multiply R / M32 by 2, Cl T
IMESC1 / 4 IB SHL R / M32, IMM8 MULTIPLY R / M32 BY 2, IMM8 TIMESD0 / 5 SHR R / M8 BY 2, ONCED2 / 5 SHR R / M8, CL Unsigned Divide R / M8 BY 2, CL Timesc0 / 5 Ib SHR R / M8, IMM8 Unsigned Divide R / M8 BY 2, IMM8 TIMESD1 / 5 SHR R / M16, 1 Unsigned Divide R / M16 by 2, ONCED3 / 5 SHR R / M16, CL UNSIGNED DIVIDE R / M16 by 2, CL Timesc1 / 5 Ib SHR R / M16, IMM8 Unsigned Divide R / M16 by 2, IMM8 TIMESD1 / 5 SHR R / M32, 1 UNSIGNED DIVIDE R / M32 BY 2, ONCED3 / 5 SHR R / M32 , CL Unsigned divide r / m32 by 2, CL timesC1 / 5 ib SHR r / m32, imm8 Unsigned divide r / m32 by 2, imm8 times1C ib SBB AL, imm8 Subtract with borrow imm8 from AL1D iw SBB AX, imm16 Subtract with borrow IMM16 from AX1D ID SBB EAX, IMM32 Subtract with Borrow IMM 32 from Eax80 / 3 IB SBB R / M8, IMM8 Subtract with Borrow IW SBB R / M16, IMM16 Subtract with Borrow IMM16 from R / M1681 / 3 ID SBB R / M32, IMM32 Subtract with Borrow IMM32 From R / M3283 / 3 IB SBB R / M16, IMM8 Subtract with Borrow Sign-Extended IMM8 from R / M1683 / 3 IB SBB R / M32, IMM8 Subtract with Borrow Sign-Extended IMM8 from R / M3218 / R SBB R / M8 , R8 Subtract with Borrow R / M16, R16 Subtract with Borrow R16 from R / M1619 / R SBB R / M32, R32 Subtract with Borrow R32 from R / M321A / R SBB R8, R / M8 Subtract with Borrow R / M8 from R81B / R
SBB R16, R / M16 Subtract with Borrow R / M16 from R161B / R SBB R32, R / M32 Subtract with Borrow R / M32 from R32ae SCAS M8 COMPARE Al with Byte At ES: (E) DI AND SET STATUS FLAGSAF SCAS M16 COMPARE AX with Word At Es: (e) Di and Set Status Flagsaf SCAS M32 Compare EAX WITH DOUBLORD AT ES (E) DI AND SET STATUS FLAGSAE SCASB Compare Al with Byte At Es: (e) Di and Set Status Flagsaf ScASW Compare AX with Word at es: (e) Di and set status flagsaf scaSD Compare ES with DoubleWord At Es: (e) Di and set status flags0f 97 seta r / m8 set byte if Above (cf = 0 and zf = 0) 0f 93 setae r / M8 set byte if Above or equal (cf = 0) 0f 92 setb r / m8 Set byte if below (cf = 1) 0f 96 setbe r / m8 set byte if Below or equal (cf = 1 or zf = 1) 0f 92 setc r / m8 set if carry (cf = 1) 0f 94 STE R / M8 Set byte if equal (zf = 1) 0f 9f setg r / m8 set byte if Greater (zf = 0 and sf = of) 0f 9d setge r / m8 set byte if Greater or equal (sf = of) 0f 9c setl r / M8 set byte if less (s> of) 0f 9e setle r / m8 set byte if less or = 1 or sf <> of) 0f 96 setna r / m8 set byte if not above (cf = 1 or zf = 1) 0f 92 setnae r / m8
Set byte if not above or equal (cf = 1) 0f 93 setNB R / M8 set byte if not below (cf = 0) 0f 97 setNbe r / m8 set byte if not beelow or equal (cf = 0 and zf = 0) 0f 93 setNC R / M8 set byte if not carry (cf = 0) 0f 95 setne r / m8 set byte if not equal (zf = 0) 0f 9e setng r / m8 set byte if not get
From r16 in from the right0f A5 SHLD R / M16, R16, CL SHIFT R / M16 TO LEFT CL Places While Shifting Bits from R16 in from the Right0F A4 SHLD R / M32, R32, IMM8 Shift R / M32 TO Left Imm8 Places While Shifting bits from r32 in from the Right0F A5 SHLD R / M32, R32, CL SHIFT R / M32 TO LEFT CL Places While Shifting Bits from R32 in from the Right 0F AC SHRD R / M16, R16, IMM8 Shift R / M16 TO RIGHT IMM8 Places While Shifting Bits from R / M16, R16, CL Shift R / M16 TO Right Cl Places While Shifting Bits from R16 in from the Left0F AC Shrd R / M32, R32, MM8 Shift R / M32 To Right Imm8 Places While Shifting Bits From r32 in from the left0f ad shrd R / M32, R32, CL SHIFT R / M32 TO RIGHT CL Places While Shifting Bits from R32 in from the Left 66 0F C6 / R IB ShuFPD XMM1, XMM2 / M128, IMM8 Shuffle Packed Double- Precision floating-point value selected by imm8 from xmm1 and xmm1 / m128 to xmm1. 0f C6 / R IB SHUFPS XMM1, XMM2 / M128, IMM8 shuffle Packed Single-Precision Floating-Point Values SELECT
ED by imm8 from xmm1 and xmm1 / m128 to xmm1. 0f 00/0 SLDT R / M16 Store Segment Selector from LDTR in R / M160F 00/0 SLDT R / M32 Store Segment Selector from LDTR in Low-Order 16 BITS OF R / M320F 01/4 SMSW R / M16 Store Machine Status Word TO R / M160F 01/4 SMSW R32 / M16 Store Machine Status Word IN LOW-ORDER 16 BITS OF R32 / M16; High-Order 16 BITS OF R32 Arefined 66 0F 51 / R SQRTPD XMM1, XMM2 / M128 Computes Square Roots of The Packed Double-Precision Floating-Point Values in XMM2 / M128 and Stores The Results in XMM1. 0f 51 / R SQRTP S xmm1, xmm2 / m128 Computes square roots of the packed single-precision floating-point values in xmm2 / m128 and stores the results in xmm1. F2 0F 51 / r SQRTSD xmm1, xmm2 / m64 Computes square root of the low double-precision FLOATING-POINT VALUE IN XMM2 / M64 and Stores The Results in XMM1. F3 0F 51 / R SQRTSS XMM1, XMM2 / M32 Computes Square Root of the Low Single-Precision Floating-Point Value In XM2 / M32 and
. Stores the results in xmm1 F9 STC SET CF flagFD STD SET DF flagFB STI SET interrupt flag; external, maskable interrupts enabled at the end of the next instruction 0F AE / 3 STMXCSR m32 Store contents of MXCSR register to m32.AA STOS m8 Store Al at Address Es: (e) Diab StoS: (e) Diab Stos M32 Store Eax At Address ES: (E) Diaa StoSb Store Al at Address ES: (E) DIAB StoSw Store Ax At Address ES : (E) Diab Store Eax At Address ES: (E) DI0F 00/1 STR R / M16 Store Segment Selector from TR in R / M162C IB SUB AL, IMM8 Subtract IMM8 from AL2D IW Sub AX, IMM16 Subtract Imm16 from AX2D ID SUB EAX, IMM32 Subtract IMM32 from EAX80 / 5 IB SUB R / M8, IMM8 Subtract IMM8 from R / M881 / 5 IW SUB R / M16, IMM16 Subtract IMM16 from R / M1681 / 5 ID SUB R / M32, IMM32 Subtract IMM32 from R / M3283 / 5 Ib SUB R / M16, IMM8 Subtract Sign-Extended IMM8 from R / M1683 / 5 IB SUB R / M32, IMM8 Subtract SIGN-EXTENDED IMM8 from R / M3228 / R SUB R / M8, R8 SUBTRACT R8 from R / M829 / R SUB R / M16, R16 SUBTRACT R16 FROM R / M1629 / R SUB R / M32, R32
Subtract R32 from R / M322A / R SUB R8, R / M8 SUBTRACT R / M8 FROM R82B / R SUB R / M16 FROM R162B / R SUB R32, R / M32 SUBTRACT R / M32 from R3266 0F 5C / r SUBPD xmm1, xmm2 / m128 Subtract packed double-precision floating-point values in xmm2 / m128 from xmm1. 0F 5C / r SUBPS xmm1 xmm2 / m128 Subtract packed single-precision floating-point values in xmm2 / mem from xmm1. F2 0F 5C / r SUBSD xmm1, xmm2 / m64 Subtracts the low double-precision floating-point values xmm2 / mem64 from xmm1 in. F3 0F 5C / r SUBSS xmm1, xmm2 / m32 Subtract the lower single-precision floating-point values in xmm2 / M . 32 from xmm1 0F 34 SYSENTER Fast call to privilege level 0 system procedures0F 35 SYSEXIT Fast return to privilege level 3 user code.A8 ib TEST AL, imm8 AND imm8 with AL; set SF, ZF, PF according to resultA9 iw TEST AX, IMM16 and IMM16 with AX; SET SF, ZF, PF According To Resulta9 ID Test Eax, IMM32 and Imm32 with Eax; Set sf, ZF, PF According To Resultf6 / 0 IB Test R / M8, IMM8 and IMM8 with R / M8; SET SF, ZF, PF According to Resultf7 / 0 IW Test R / M16, IMM16 and IMM16 with R / M16; SET SF, ZF, PF According to Resultf7 / 0 ID Test R / M32, I
MM32 and IMM32 with R / M32; SET SF, ZF, PF According to Result84 / R Test R / M8, R8 and R8 with R / M8; SET SF, ZF, PF According To Result85 / R Test R / M16, R16 and R16 WITH R / M16; SET SF, ZF, PF According To Result85 / R Test R / M32, R32 and R32 With R / M32; SET SF, ZF, PF According to Result66 0F 2E / R Ucomisd XMM1, XMM2 / M64 Compares (unordered) the low double-precision floating-point values in xmm1 and xmm2 / m64 and SET the EFLAGS accordingly. 0F 2E / r UCOMISS xmm1, xmm2 / m32 Compare lower single-precision floating-point value in xmm1 register with lower single- . 0F 0B UD2 Raise invalid opcode exception66 0F 15 / r UNPCKHPD xmm1, xmm2 / m128 Unpacks and Interleaves double-precision floating-point values from high quadwords of xmm1 and xmm2 / m128. 0F 15 / r UNPCKHPS xmm1, xmm2 / m128 Unpacks and Interleaves SINGLE-PRECISION FLOATING-POINT VALUES from High QUADWORDS OF XMM1 and XMM2 / MEM INTO XMM1. 66 0F 14 / R UNPCKLPD XMM1, XMM2 / M128 Unpacks and Inter
leaves double-precision floating-point values from low quadwords of xmm1 and xmm2 / m128. 0F 14 / r UNPCKLPS xmm1, xmm2 / m128 Unpacks and Interleaves single-precision floating-point values from low quadwords of xmm1 and xmm2 / mem into xmm1. 0F 00/4 VERR R / M16 SET ZF = 1 if Segment Specified with R / M16 Can Be Read0F 00/5 Verw R / M16 SET ZF = 1 IF Segment Specified with R / M16 Can Be Written9b Wait Check Pending Unmasked Floating-Point Exceptions.9b fwait check peck poodning unmasked floating-point exceptions.0f 09 WBINVD Write back and flush Internal caches; initiate writing-back and flushing of external caches 0F 30 WRMSR Write the value in EDX:. EAX to MSR specified by ECX0F C0 / r XADD r / m8, r8 Exchange r8 and r / m8; load SUM INTO R / M8.0F C1 / R XADD R / M16, R16 Exchange R16 and R / M16; LOAD SUM INTO R / M16.0F C1 / R XADD R / M32, R32 Exchange R32 And R / M32; Load Sum Into R / M32.90 RW XCHG AX, 16 Exchange R16 with AX90 RW XCHG R16, X Exchange AX with R1690 RD XCHG EAX, R32 E
XChange R32 with EAX90 RD XCHG R32, EAX Exchange Eax with R3286 / R XCHG R / M8, R8 Exchange R8 (Byte Register) with byte from R / M886 / R XCHG R8, R / M8 Exchange Byte from R / M8 with R8 (Byte Register) 87 / R XCHG R / M16, R16 Exchange R16 with Word from R / M1687 / R XCHG R16, R / M16 Exchange Word from R / M16 with R1687 / R XCHG R / M32, R32 Exchange R32 with Doubleword from FROM R / M3287 / R XCHG R32, R / M32 Exchange Doubleword from R / M32 with R32D7 XLAT M8 SET Al to Memory Byte DS: [(E) BX Unsigned Al] D7 XLATB SET Al to Memory Byte DS: [(E) BX unsigned al] 34 IB xor al, IMM8 Al XOR IMM835 IW xor AX, IMM16 AX XOR IMM1635 ID XOR EAX, IMM32 EAX XOR IMM3280 / 6 IB XOR R / M8, IMM8 R / M8 XOR IMM881 / 6 IW XOR R / M16, IMM16 R / M16 XOR IMM1681 / 6 ID XOR R / M32, IMM32 R / M32 XOR IMM3283 / 6 IB XOR R / M16, IMM8 R / M16 XOR IMM8 (SIGN-EXTENDED 83/6 IB XOR R / M32, IMM8 R / M32 XOR IMM8 (SIGN-EXTENDED) 30 / R XOR R / M8, R8 R / M8 XOR R831 / R XOR R / M16, R16 R / M16 XOR R1631 / R XOR R / M32, R32 R / M32 XOR R3232 / R XOR R8, R / M8 R8 XOR R / M833 / R XOR R / M833 / R XOR R32, R / M32 R32 XOR R / M866 0F 57 / R XORPD XMM1, XMM2 / M128 Bitwise Exclusive-or Off 57 / R XORPS XMM1, XMM2 / M128 Bitwise Exclusive-or OR of XM2 / M128 and X
MM1. Instruction prefix:
ES: 26 ES section spans the prefix
CS: 2e CS section spans the prefix
SS: 36 SS segment spans the prefix
DS: 3e DS section spans the prefix
FS: 64 FS section spans the prefix
GS: 65 GS section spans the prefix
Opsize: 66 Operament Type Cross the prefix
Address: 67 address type spans prefix
Description of the symbol used in the above instructions:
/ DIGIT - Digital between 0 to 7, used to use the mod / m byte of the command of the register / memory operation, as the instruction spread code
/ r - indicates that the ModR / M byte of the instruction contains both register operands, but also contains memory operations.
CB - byte offset value relative to the next instruction
CW - word offset relative to the next instruction
CD - double-word offset value relative to the next instruction
CP - absolute far pointer
IB, IW, ID - IB: 1 byte immediately; IW: 2 bytes Immediately; ID: 4 bytes
RB, RW, RD - Register code, from 0 to 7, is added to the operating number:
RB RW RD
----------------------
Al = 0 AX = 0 EAX = 0
CL = 1 CX = 1 ECX = 1
DL = 2 dx = 2 EDX = 2
BL = 3 bx = 3 EBX = 3
AH = 4 sp = 4 ESP = 4
CH = 5 bp = 5 EBP = 5
DH = 6 Si = 6 ESI = 6
BH = 7 di = 7 EDI = 7
i - Digital for floating point instructions, indicating one of ST (i)
REL8 - 8 bit relative address, range: -128 ~ 127
REL16, REL32 - relative address in the same paragraph
PTR16: 16, PTR16: 32 - Farming, typical application to cross-block instructions
R8 - 8 universal register
R16 - 16-bit universal register
R32 - 32-bit universal register
IMM8 - 8-bit immediate number
IMM16 - 16-bit immediate number
IMM32 - 32-bit immediate number
R / M8 - 8-bit universal register or memory byte
R / M16 - 16-bit universal register or memory byte
R / M32 - 32-bit universal register or memory byte
M - 16 or 32-bit memory operation
M8 - memory byte by DS: (E) Si or ES: (E) DI
M16 - memory word pointing by DS: (e) Si or ES: (E) DI
M32 - Memory Double Words Pointing by DS: (E) Si or ES: (E) DI
M64 - memory four words, only for CMPXCHG8B instructions
M16: 16, M16: 32 - Contains the number of memory pointer operators, the quotation number is the segment address, and the offset address is behind the quotation marks.
M16 & 32, M16 & 16, M32 & 32 - Contains data pair memory operand
MOFFS8, MOFFS16, MOFFS32 - Indicates the type of byte, word, and double word, respectively.
SREG - segment register, ES = 0, CS = 1, SS = 2, DS = 3, FS = 4, GS = 5
M32REAL, M64REAL, M80REAL - single precision, double precision, expansion double precision memory floating point operation
M16INT, M32INT, M64INT - Dip type, double font, quadruple memory integer operand
St or St (0) - FPU Register Stack Stack Top Element
ST (i) - I = 0, 1, 2, 3, 4, 5, 6, 7 from the number of FPU register stacks, i = 0, 1, 2, 3, 4, 5, 6, 7
MM - MMX register, from MM0 to MM7
MM / M32 - MMX register low 32-bit or 32-bit memory operand
MM / M64 - MMX register or 64-bit memory operand
XMM - 128-bit XMM register, from xmm0 to xmm7
XMM / M32 - XMM register or 32-bit memory operand
XMM / M64 - XMM register or 64-bit memory operand
XMM / M128 - XMM register or 128-bit memory operand
