Memory Management under Intel Architecture
--- Memory Management in Protection Modes from Intel CPU
Excerpted from: http://perdubug.go.nese.net/htmls/note/Memory_Management.htm Process and Thread: http://perdu.go.nease.Net/htmls/theory/multitasking.htm# Win32 In stack : http://perdubug.go.nese.Net/htmls/win32/win32stack.htm# 2004.8.31 night, read the e-book written by Bill Blunden << Memory Managing Algorithms and Implementation In C / C >>, At the beginning, I thought it was written in C , so I was wrong to my C directory. The first writing of this book is written by memory management mechanism, it is very good, honestly said some of them. The content I should read the << Windows95 Developer Guide to read Stefano Maruzzi a few years ago, it should be understood, but unfortunately, the translation of the book makes me really don't understand, I am fortunate to see it today. This book makes me not on this piece of knowledge gap, fortunate, fortunately ... summarize the first: I have to understand that memory management should be very difficult, I can imagine the way to have two: from hardware angle Go to understand, see what kind of mechanism provides the mechanism to support memory management; from the perspective of operating system, see how the operating system uses hardware to provide the mechanism to implement its own memory management; my grass written this The article mainly wants to have a correct understanding and understanding from the hardware perspective ... Intel Architecture supports both direct physical addressing to memory (by page mechanism), in physical addressing mode Linear addresses are equivalent to a physical address, all of the code, data, stack, system segment (segment), GDT (global descriptor table), IDT (interrupt descriptor table), only recently visited The page will remain in physical memory. The location of the page in the physical memory (this page is called page frame under Intel Architecture) is labeled by two system data structures: a page directory, a pile of pages (note, page directory and page table will always stay In physical memory): 1. The information contained in a entry in the page directory includes: a page table physical base address, access permission, and some other memory management information. 2. The information contained in a entry in the page table includes: a physical address, access permissions, and other memory management information for a Page Frame. What exists in the base address of the page directory? There is a CR3 register, which is a system register. In order to use the page mechanism, a linear address is divided into three parts: 1, the data pointed to by this address in an offset address in a certain page frame, the offset address of the Page Frame mentioned above 3. The page table mentioned above is in the offset address in the page directory; the above is sure it is very windy, see the following this picture will understand the relationship between the three people, the page table, the page table. :
A. Watch the relevant basic concepts and look at what is the descriptor table? It is similar to an array, each of the arrays is a segment descriptor; what is the segment descriptor (Segment Descriptor Descriptor? Segment Descriptor describes the properties of a segment, including the size of the segment, access rights, privileged levels, and the type of segment (data segment, code segment ...), and the basement of the segment; According to Intel: a Segment Descriptor Provides The Base Address of A Segment And Access Rights, Type, And Usage Information. There is a segment selector and it associates, Segment Descriptor (Segment Descriptor) There are 64-bit long, where is worth noting the field: 0-15 indicates the limit of the size of the memory described in this segment descriptor, the maximum should be 2 16th = 64K 16-31 The combination of this paragraph (16-bit) SS 0 system segment, 1 code, or data segment Type 4-bit, 1 Code, or Data Segment Type 4-bit, as follows: Type = Accessed This segment has just visited Type = Expand Down, this Segment is very suitable for STACK because it grows from the high address to low address growth type = confore, this segment allows the low permission code to jump to this at lower permission. Performing their code What is the SEGMENT SELECTOR? The segment selector is a unique indication of a segment, including: segment descriptor in GDT or LDT index, marker bit, access information; one segment The selector and an offset address uniquely determine a paragraph in a segment, why say this, because a segment selector can determine a segment descriptor, the segment descriptor contains the base address of the segment Of course, the base address and offset address can certainly determine one byte in the segment.
What is the segment? Segment is from a program perspective to different address space, Segment's definition in the Intel's official documentation is as follows: THIS Is A Form of Addressing Where A Program May Have Many Independent Address Spaces, Called Segments. 2 .segmentation provides a mechanism for dividing the processor's addressable memory space (called the linear address space) into smaller protected address spaces called segments.If more than one program (or task) is running on a processor, each program can be assigned its own set The information you can see from now on is: 1, the paragraph is protected, which provides a mechanism that makes each program unable to invade each other's address space; 2, the segment is from the point of view; Segmentation Mechanism and Paging Mechanism This is the two memory management mechanisms provided in Intel Architecture in protection mode. Each program / task is in its own small heavens, page management is mainly to solve the balance between memory requirements and actual physical memory; in Intel Architecture protection mode, segment management is required, but the page Management is optional, that is, to cancel the page management mechanism by some settings. The memory segmentation structure is a typical feature of Intel CPU, and other processors do not necessarily have such features, such as RISC, that is, the memory segment will be a problem that the program needs to face between different platforms.
Linear address (Linear Address) and the logical address (Logical Address) All of the segments within a system are contained in the processor's linear address space. To locate a byte in a particular segment, a logical address (sometimes called a far pointer) must be This can be seen from this information is: 1, the linear address is used to address the address space consisting of all segments, and the logical address is used to address within a segment, and since the logical address is in the segment Internal addressing, then it must contain a segment selector and an offset; physical address (Physical Address) Follow the INTEL: The Physical Address Space Is Defined as The Range of Addresses That The Processor CAN Generate On Its Address Bus. VCA Memory Memory and Page Mechanisms are page mechanisms to support the underlying guarantees of virtual memory and protection mode real mode protection mode It can be seen that the management rules of real mode are relatively simple, addressing in real mode The space is limited to 1 MB, and the real mode does not provide any memory protection mechanism. If you want to implement a valid multitasking environment, memory protection is indispensable. The fundamental difference between real mode and protection mode is different from the mechanism of accessing the memory location.
TLB (Translation Look-Aside Buffer) is equivalent to a cache that is to reduce access page directories, the number of pages, which generally do it in the CPU chip, the size is generally 64K. B. Intel Architecture In Protection Memory Management Mainly includes: Segment Management Mechanism and Page Management Mechanism We can see the logical address consisting of two parts: segment selector and offset; above we have already said that the segment selector is like Is indexing makes we can find a paragraph descriptor in GDT, through this descriptor, we can find a certain segment in the linear address space, know the offset in this segment plus the logical address, we can Get a linear address; we can set a physical address, wonderful, too wonderful, based on this linear address, wonderful ~~~~ From the above picture we can see: 1, linear address space and physical address The difference and relationship between space; 2, the logical address is a linear address space; Page Directory, Page, Page Frame, but please note that the previous sentence is premised: If the system takes a page mechanism, because we mentioned the page mechanism in front of us is optional, if the system does not use a page mechanism If the linear address to the physical address is straightforward, naked. But I personally think that this picture also has a place that needs to be considered, that is, the rightmost Page exactly said that it should be Page Frame.
The description of the page directory is as follows, some of which is worthy of 1.P is maintained by the operating system, used to indicate if this page is in the memory 2. ps page size as the page mechanism is determined by the system register CR0, the PG in Cr0 The field determines whether it takes page management, if there is no setting, 32-bit address is treated as a physical address, THE CR0 IS Used to control the processor mode and state of the processor 2.the cr1 is reserved 3.the cr2 register is used to store the linear address that has caused a page fault. 4.The CR3 plays a central role in the resolution of physical addresses when paging has been enabled 5.The CR4 register is used to enable a couple of advanced mechanisms. control example The size of the page C. Basic Flat Model and protected flat model is based on the segment management base address provided by Intel Architecture, which can build a variety of concrete memory management mode: 1.Basic Flat Model requires at least two segment selectors: one Point to the data segment, a pointing code segment; these two paragraphs point to the same 4G size linear address space; 2. PROTECTED FLAT MODEL D.INTEL ARCHITECT provides four registers for memory management First look at memory management Intel CPU gives me what kind of support, Intel Architecture provides four registers for memory management [1]: a. GDTR global descriptor table register B. IDTR interrupt descriptor table register C. TR task register d. LDTR Local Descript Table Register A. GDTR (Register of Global Description Table) consists of two parts: a 32-bit address and a 16-bit's top-length limit description, 32-bit address points to GDT, behind 1 6-bit Use to explain the length limit of this GDT; Intel provides two instructions to operate on this register: LGDT, SGDT. B. LDTR (local descriptor table) consists of two parts: a 16-bit selection A 32-bit address, a 16-bit segment long restriction description and LDT attribute information, 32-bit address points to LDT, Intel provides two instructions to operate on this register: LLDT, SLDT. Because LDT It is existing in a segment, so it is bound to have a segment descriptor in the GDT to describe this block memory.
E. Use a hidden treasure map to illustrate the above F. Leave your own problem specific to Windows, what kind of memory management mechanism is made in the mechanism provided by Intel ArchiteCte? 1.FLAT Address Space only has a 4G segment in Windows NT, which means that the operating system is in this 4G linear address space, then use the paging mechanism to solve the linear address space and physical memory. Balance problem; in this 4G space, low 2G is the user address space, high 2G is kernel address space; how did this 4G come? I used to know CS, DS, ES, SS four-segment in 32-bit, and SS, segment: Offset is useful, and 32-bit OFFSET can address 4G space, the answer is completed. 2.Process isolation Winnt's way to implement the process by maintaining a page directory (Page Directory), wonderful; but there is a question: That Kernel section? How can the process visit these kernel sections? In WinNT, the Kernel section is placed in the Kernel page, which is a special page (Supervisor Pages), which can be avoided within the previously mentioned page directory. User Mode Code Access Kernel. The following is a Microsoft's Windows 2000 Technical Book for explaining process isolation drawings: 3.Code Page Sharing In DLLS in WinNT, if the process m loads dynamic library X.dll (returned after loading The linear address is A1), the process N is also loaded with x.dll (the linear address returned after the load is A2), if A1 = A2 is then the physical address pointed to by A2 is the same physical address; that is, the dynamic library is Placed in a shared space and is read-only to prevent modification of the application. 4.Context Switching The Act of Stopping A Thread at the end of stopping a thread at the end of its time slice and scheduing another thread is called context switching. The overhead of the context switch is obvious: refresh the TLB overhead; if the two thread belongs to the same If the process, the TLB can also help us save a little overhead, because the TLB is still used, but if the two threads belong to different processes, then the linear addresses of Cache in TLB are not used (because it belongs to another process) Address space), that is, TLB can't play, at this time, you need to refresh TLB. Switching in context is required to save and overload the following data: 1. Program counter; processor status register; 3. Content of other registers; 4. IUSER and KERNEL stacks; 5. Point to the pointer to the page directory because each One process has its own page directory so you want to keep your own pointer;
