Makefile's summary -------
First, what is Makefile?
Makefile mainly includes five things: explicit rules, murgee rules, variable definitions, file instructions, and comments.
1. Explicit rules. Explicit rules illustrate how to generate one or more target files. This is clearly pointed out by Makefile's writing, the file, dependent file, the generation of the file, the resulting command.
2, the macious rules. Since our makers have automatic derived features, the concealed rules allow us to write Makefile relatively roughly, which is supported by Make.
3, the definition of the variable. In Makefile, we want to define a series of variables, the variables are generally strings, this a bit in your C language macro, when Makefile is executed, the variables are extended to the corresponding reference location.
4, file instructions. It includes three parts, one is to reference another Makefile in a makefile, just like include in the C language; the other means that the effective part in the makefile is specified according to some cases, just like the precompilation in the C language. #iF is the same; there is a multi-line command. I will talk about this part of the content.
5, comment. Makefile is only a row of comments, like UNIX's shell script, which comes with "#" characters, which is like "//" in C / C . If you want to use the "#" characters in your makefile, you can use the backstelvers to escape, such as "/ #".
Finally, it is also worth mentioning that in the Makefile command, you must start with the [Tab] button.
Second, Makefile's file name
By default, the make command finds the file name "gnumakefile", "makefile", "makefile", "makefile", "makefile", and found the file. In these three file names, it is best to use "makefile" file name, because this file name is the first character for uppercase, which has a dedicated feeling. It is best not to use "gnumakefile", this file is the GNU's Make recognition. There are additional Make only sensitive to the full-written "Makefile" file name, but basically, most of the Make supports "makefile" and "makefile" two default file names.
Of course, you can use other file names to write makefile, such as "make.linux", "make.solaris", "make.aix", etc. If you want to specify a specific makefile, you can use Make's "-f" And "--file" parameters such as: make -f make.linux or make --file make.aix.
Third, reference other Makefile
In Makefile Use the include keyword to include other makefiles, which is like a C language #include, the file being included in the original model is placed in the current file. Include's grammar is:
INCLUDE
FILENAME can be the file mode of the current operating system shell (you can save the path and wildcard)
There may be some empty characters in front of Include, but must never start with the [Tab] button. Include and
Equivalent to:
Include foo.make a.mk B.mk C.MK E.MK F.MK
When the make command starts, the other makefile indicated by INCLUDE is placed in the current position. Just like the #include directive of C / C . If the file does not specify an absolute path or relative path, make will first look for in the current directory, if you are not found in the current directory, then make it will find:
1. If Make is executed, there is a "-i" or "-include-dir" parameter, Make will find the directory specified by this parameter. 2, if the directory
If there is no file, make Make generate a warning message, but it will not immediately appear. It will continue to load other files. Once make Makefile's read, make will try again, or if it cannot be read, Make will only have a fatal information. If you want Make ignore those files that you can't read, continue to execute, you can add a minus "-" in front of Include. Such as:
-include
Fourth, environment variable Makefiles
If you define environment variables Makefiles in your current environment, Make will make a value in this variable similar to the Include action. The value in this variable is the other makefile, separated by spaces. However, it is different from the include that "target" from the Makefile introduced from this environment will not work. If the file defined in the environment variable finds an error, Make will ignore.
But here I still recommend not using this environment variable, because as long as this variable is defined, when you use Make, all Makefile will be affected by it, this is not what you want to see. Here, this is just to tell you, maybe sometimes your makefile has a strange thing, then you can see if this variable is defined in the current environment.
V. Make's work
The execution steps of GNU's Make work will be entered: (I want to come to other Make.)
1. Read all Makefile. 2, read into other Makefiles of include. 3. Initialize the variables in the file. 4. Divide the murchest rules and analyze all rules. 5. Create a dependency chain for all target files. 6. Depending on the dependencies, decide which goals should be regenerated. 7, execute the generated command.
1-5 Steps to the first stage, 6-7 is the second phase. In the first phase, if the defined variable is used, Make will expand it in the location where it is used. But Make will not completely start immediately. Make uses delay tactics. If the variable appears in the rules of dependencies, then the variable is only expanded within it only when this reliance is determined. Of course, this way you don't have to be clear, but you know this way you will be more familiar with Make. With this foundation, the subsequent part is easy to understand.
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