Writing command ----
Command lines of each rule and the command line of the operating system shell are consistent. Make will execute a command in order, each command must begin with the [Tab] key, unless, the command is followed by the semicolon behind the dependency rule. The space in the command line or the blank line will be ignored, but if the space or the blank line is opened with a Tab key, Make will think it is an empty command.
We can use different shells under UNIX, but make the make commands are performed by the "/ Bin / SH" - UNIX standard shell. Unless you specifically specify a further shell. Makefile, "#" is an comment, very like "//" in C / C , and the subsequent bank characters are commented.
First, display command
Typically, Make will output the command line to be executed before the command is executed on the screen. When we use the "@" character before the command line, then this command will not be displayed by Make, the most representative example, we use this feature to display some information on the screen. Such as:
@echo is compiling XXX modules ...
When Make is executed, the "compiling the XXX module ..." string is output, but the command is not output, if there is no "@", then make will output:
Echo is compiling XXX modules ... is compiling XXX modules ...
If Make is executed, bring the Make parameter "-n" or "--just-print", then it just displays the command, but does not execute the command, this feature is very good for us to debug our makefile, see what we write The command is what is executed or what is the order.
The Make parameter "-s" or "--slient" is a full disable command display.
Second, the command execution
When relying on the target is new in the target, the Make will execute the subsequent command when the target of the rule needs to be updated. It should be noted that if you want to apply the result of the previous command to the next command, you should use the semicolon to separate these two commands. For example, your first command is a CD command, you want the second command to run on the CD, then you can't write these two commands on both lines, but should write these two commands. On a row, separated by a semicolon. Such as:
Example 1: EXEC: CD / HOME / HCHEN PWD
Example 2: EXEC: CD / Home / Hchen; PWD
When we perform "make exec", the CD in the first example does not work. The PWD will print the current makefile directory, and in the second example, the CD works, and the PWD will print "/ HOME / HCHEN ".
Make is typically executing commands using the system shell defined in the environment variable shell, by default, using UNIX standard shell - / bin / sh to execute the command. But it is a bit special under MS-DOS because there is no shell environment variable under MS-DOS, of course you can also specify. If you specify the form of a UNIX style, first, Make will find a command interpreter in the path specified by Shell. If you can't find it, you will find it in the current directory in the current drive, if you can't find it, It will be found in all paths defined in the PATH environment variable. In MS-DOS, if your defined command interpreter is not found, it will give you a command interpreter, such as ".exe", ". Com", ".", ". Sh", etc.
Third, the order is wrong
Whenever the command is running, make detects the return code of each command. If the command returns success, then make will perform the next command. When all the commands in the rules have been successfully returned, this rule is completed. If a command in a rule is wrong (the command exits is not zero), the make will terminate the execution of the current rule, which will be possible to terminate all rules. Sometimes, the error of the command does not mean that it is wrong. For example, the mkdir command, we must build a directory, if the directory does not exist, then MKDIR will be executed successfully, and all the best, if the directory exists, then it is wrong. The reason why we use MKDIR is to have such a directory, so we do not want MKDIR to go wrong and terminate the rules.
In order to do this, ignore the error of the command, we can add a minus "-" (after the Tab key) in the Makefile command line, the tag is not that the command is not wrong. Such as:
Clean: -rm -f * .o
There is also a global way to add "-i" or "--ignore-errors" parameters to make, then all commands in makefile ignore errors. And if a rule is ".ignore" as a target, all commands in this rule will ignore the error. These are methods of preventing an error in different levels, you can set it according to your different.
There is also a "-k" or "--keep-going", which is "-k" or "--keep-going", this parameter is that if the command in a rule is wrong, then the execution of the rule, But continue to perform other rules.
Fourth, nested to execute Make
In some big projects, we will put our different modules or different functional files in different directories, we can write a directory of Makefile in each directory, which is conducive to let our makefile change It is more concise, not to write all things in a makefile, which will hardly maintain our makefile, which has a very benefit of our module compilation and segmentation compilation.
For example, we have a subdirectory called subdir. There is a Makefile file in this directory to indicate the compilation rules for the files in this directory. Then our total control Makefile can write like this:
Subsystem: CD Subdir && $ (MAKE)
It is equivalent to:
Subsystem: $ (MAKE) -C Subdir
Defining $ (Make) macro variable means that perhaps our make needs some parameters, so defined as a variable is also conducive to maintenance. These two examples means to enter the "subdir" directory first, then execute the make command.
We call this Makefile ", the total control Makefile" can be passed to the subkey Makefile (if you show the declaration), but will not cover the variable defined in the subkefile of the next layer, unless specified "-e "parameter.
If you want to pass a variable into a sub-Makefile, then you can use this statement:
EXPORT
If you don't want some variables to be delivered to the sub-Makefile, then you can declare this:
UNEXPORT
Such as: Example 1:
Export variable = value
It is equivalent to:
Variable = Value Export Variable is equivalent to:
Export variable: = value
It is equivalent to:
Variable: = Value Export Variable
Example 2:
Export variable = Value
It is equivalent to:
Variable = Value Export Variable
If you want to pass all variables, then just an export. There is no need to follow, indicating that all variables are passed.
It should be noted that there are two variables, one is the shell, one is makeflags, these two variables don't care if you export, it is always necessary to pass to the next Makefile, especially the makefiles variable, which contains the parameter information of Make, If we have a Make parameter or define this variable in the upper Makefile when performing "Total Makefile", the makefiles variable will be these parameters and will be transferred to the lower Makefile, which is a system-level environment variable.
However, several parameters in the make command are not transmitted down, they are "-c", "- f", "- h" "- o" and "-w" (detail about the Makefile parameter will be described later. ), If you don't want to pass parameters to the lower layer, then you can come:
Subsystem: CD Subdir && $ (Make) Makeflags =
If you define environment variables makeflags, then you have to be confident that everyone will be used, if there are "-t", "- n", and "-q" parameters, then there will be unexpected The result may make you panic.
There is also a more useful parameter, "- w" or "-print-directory" in "Nesting Execution", which will output some information in the opportunity of Make, so that you see the current working directory. For example, if our subordinate Make directory is "/ home / hchen / gnu / make", if we use "make -w" to execute, we will see when entering the directory, we will see:
Make: Entering Directory `/ Home / Hchen / GNU / Make '.
When you leave the directory after completing the subkey, we will see:
LEAVING DIRECTORY `/ Home / Hchen / GNU / Make '
When you use the "-c" parameter to specify the next Makefile, "- W" will be turned on automatically. If there is "-s" ("- slient") or "--no-print-directory" in the parameter, "- w" is always invalid.
V. Define the command package
If there are some same command sequences in Makefile, we can define a variable for these same command sequences. Defining the syntax of this command sequence begins with "Define", end with "endef", such as:
Define Run-Yacc Yacc $ (Firstword $ ^) mv y.tab.c $ @ Endef
Here, "run-yacc" is the name of this command package, which does not reintegrate with the variables in Makefile. Two lines in "define" and "endef" are command sequences. The first command in this command package is running the YACC program because the YACC program always generates "Y. Tab.c" files, so the second line command is to change this file. Or put this command to a sample to see it. FOO.c: foo.y $ (run-yacc)
We can see that we want to use this command package, we seem to use variables. In this command package, "$ ^" in the command package "Run-Yacc" is "foo.y", "$ @" is "foo.c" (related to this special variable starting with "$" We will introduce later), Make is executing each command in the command package when executing the command package.
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