Sixth, multi-line variables There is also a way to set variable values to use the define keyword. The value of setting the variable using the define keyword can have a wrap, which facilitates the definition of a series of commands (before we told the "command package" technology to use this keyword).
The define indicator is followed by the name of the variable, and restarts the value of the defined variable, the definition is the end of the Endef keyword. Its work mode is the same as the "=" operator. The value of the variable can contain functions, commands, text, or other variables. Because the command needs to begin with the [Tab] key, if you don't start with the [Tab] button with the defined command variable, Make will not think it is a command.
The following example shows the usage of Define:
Define Two-Lines Echo Foo Echo $ (BAR) Endef
Seven, environment variables
Make runtime system environment variables can be loaded into the Makefile file while Make starts, but this variable has been defined in Makefile, or this variable is brought by the Make command line, then the value of the environmental variable of the system will Covered. (If Make specifies the "-e" parameter, the system environment variable will override the variables defined in Makefile)
Therefore, if we set the "cflags" environment variable in the environment variable, we can use this variable in all Makefiles. This has a relatively good benefit to our compilation parameters. If you define cflags in makefile, this variable in makefile will use the value of the system environment variable, a common and personalized unity, which is very similar to the "global variable" and "local variable" if it is not defined.
When Make nested (see chapter "Nested Call chapter), the variable defined in the upper Makefile will be passed to the lower Makefile in the way system environment variables. Of course, by default, the variables set by the command line will be passed. And define the variables in the file, if you want to pass down MakeFile, you need to use the exprot keyword to declare. (See the previous section)
Of course, I don't recommend that many variables are defined in the system environment, so that when we don't have to make Makefile, it has the same system variable, which may bring more trouble.
Eight, target variables
The variables we defined in Makefile before we are talking about are "global variables", and we can access these variables throughout the file. Of course, except "automated variables", such as "$ <", such as "$ <" belongs to the "rule variable", and the value of this variable depends on the rules and definitions of dependent targets.
Of course, I can also set local variables for a target. This variable is called "target-specific variable", which can be with "global variable", because its role range is only in this rule and the joint rules Therefore, its value is only valid within the scope of action. The value of global variables other than the rule chain will not affect the rule chain.
Its syntax is:
This feature is very useful, when we set a variable, this variable will act to all rules caused by this goal. Such as: prog: cflags = -g prog: prog.o foo.o bar.o $ (cc) $ (cflags) prog.o foo. bar.o
Prog.O: Prog.c $ (cc) $ (cflags) prog.c
FOO.O: FOO.C $ (CC) $ (cflags) foo.c
Bar.o: bar.c $ (cc) $ (cflags) bar.c In this example, regardless of the value of the global $ (cflags), in the PROG target, and all the rules that it raind (PROG. O foo.o bar.o rules), the value of $ (cflags) is "-g"
Nine, pattern variable
In the GNU's Make, the pattern variable is also supported. In the above target variable, we know that variables can be defined on a certain target. The advantage of mode variables is that we can give a "mode" to define variables on all targets that meet this mode.
We know that Make's "mode" is generally at least one "%", so we can define target variables in [.o] at the end of [.o] as follows:
% .o: cflags = -O
Similarly, the syntax and "target variable" of the mode variable:
OVERRIDE is also a variable that is incorporated on the system environment, or the variable specified by the Make command line.
Conditions judgment ------
Using conditional judgment, Make can make Make selection different execution branches depending on the time of runtime. The conditional expression can be a value of a comparison variable, or a value of comparison variables and constants.
First, example
The following example, determine if the $ (cc) variable "GCC", if yes, use the GNU function to compile the target.
Libs_for_gcc = -lnu normal_libs =
Foo: $ (Objects) IFEQ ($ (CC), GCC) $ (CC) -O Foo $ (Objects) $ (Libs_for_GCC) ELSE $ (CC) -o Foo $ (Objects) $ (NORMAL_LIBS) ENDIF
It can be seen that in this rule in the example above, the target "foo" can select different libraries to compile the program according to the variable "$ (cc) value value.
We can see three keywords from the above example: IFEQ, Else, and Endif. IFEQ means the beginning of the conditional statement, and specifies a conditional expression, the expression contains two parameters, separated by commas, and the expression is enclosed in parentheses. Else indicates the condition of the conditional expression. Endif indicates the end of a conditional statement, and any conditional expression should end with ENDIF.
When our variable $ (cc) value is "GCC", the rules of the target foo are:
Foo: $ (OBJECTS) $ (CC) -o foo $ (ibjects) $ (libs_for_gcc)
And when our variable $ (cc) value is not "GCC" (such as "cc"), the rules of the target foo are:
Foo: $ (OBJECTS) $ (cc) -o foo $ (ibjects) $ (Normal_Libs) Of course, we can also write the above example more concise:
Libs_for_gcc = -lnu normal_libs =
IFEQ ($ (CC), GCC) libs = $ (libs_for_gcc) Else Libs = $ (NORMAL_LIBS) ENDIF
Foo: $ (Objects) $ (CC) -O Foo $ (Objects) $ (LIBS)
Second, grammar
The syntax of the conditional expression is:
as well as:
Where
The first is "IFEQ" you have seen in front.
IFEQ (
The value of comparison parameters "arg1" and "arg2" are the same. Of course, we can also use the Make function in the parameter. Such as:
IFEQ ($ (Strip $),)
The "strip" function is used in this example. If the return value of this function is empty, then
The second condition key is "ifneq". The syntax is:
IFNEQ (
Its comparison parameter "arg1" and "arg2" are the same, if different, it is true. Similar to "IFEQ".
The third condition key is "IFDEF". The syntax is:
IFDEF
If the value of the variable
Example 1: BAR = foo = $ (bar) ifdef foo frobozz = yes else frobozz = no endif example: foo = ifdef foo frobozz = yes else frobozz = no endif
In the first example, the "FROBOZZ" value is "YES", and the second is "NO".
The fourth condition key is "ifndef". Its syntax is:
IFNDEF
I don't have much to say this, and "ifdef" is the opposite.
On
In particular, Make is the value of the conditional expression when reading Makefile, and selects the statement according to the value of the conditional expression, so don't put the automated variables (such as "$ @", etc.) In the conditional expression, since the automation variable is only running.
Moreover, in order to avoid confusion, MAKE does not allow the entire condition statement into two parts in different files.
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