1, data transfer command
1.1, transfer instruction
The syntax of the instruction is a number of MOV REG, REG MOV BP, SP 1 MOV MEM, REG MOV ARRAY [DI], BX 1 MOV REG, MEM MOV BX, POINTER 1 MOV MEM, IMMED MOV [BX], 15 1 MOV REG, Immed MOV CX, 256 1 MOV MEM, Accum Mov Total, AX 1 MOV Accum, MEM MOV AL, STRING 1 MOV Segreg, Reg16 MOV DS, AX 2, 3 MOV Segreg, MEM16 MOV ES, PSP 2, 3 MOV REG16, SegReg MOV AX, DS 1 MOV MEM16, Segreg Mov Stack_save, SS 1 MOV REG32, ControlReg Mov Eax, Cr0 22 MOV EAX, CR2 12 MOV Eax, CR3 21, 46 MOV Eax, CR4 14 MOV ControlReg, Reg32 MOV CR0, EAX 4 MOV REG32, DEBUGREG MOV EDX, DR0 DR0-DR3, DR6, DR7 = 11 DR4, DR5 = 12 MOV DEBUGREG, REG32 MOV DR0, ECX DR0-DR3, DR4, DR5 = 12 DR6, DR7 = 11
1.2, transfer - padding instruction
Movsx REG, REG MOVSX BX, Al 3 Movsx REG, MEM MOVSX EAX, BSIGN 3 MOVZX REG, REG MOVZX BX, AL 3 MOVZX REG, MEM MOVZX EAX, BUNSIGN 3
1.3, exchange instruction
XCHG REG, REG XCHG CX, DX 3 XCHG REG, MEM XCHG BX, POINTER 3 XCHG MEM, REG XCHG [BX], AX 3 XCHG Accum, REG XCHG AX, CX 2 XCHG, Accum XCHG CX, AX 2
1.4, segment address and valid address instruction
LDS REG, MEM LDS SI, FPOINTER 4 LES REG, MEM LES DI, FPOINTER 4 LFS REG, MEM LFS EDI, FPOINTER 4 LGS REG, MEM LGS BX, FPOINTER 4 LSS REG, MEM LSS BP, FPOINTER 4, PM = 8 LEA REG, MEM LEA BX, NPOINTER 1
1.5, inrest
Push Reg Push [Di] 2 Push Segreg Push ES 1 Push Immed Push 15000 1 Pushha Push 5 Pushad Pushad 5 Pushf Pushf 4, PM = 3 Pushfd Pushfd 4, PM = 3
1.6, out of the stack
POP REG POP CX 1 POP MEM POP Param 3 Pop Segreg Pop ES 3 POPA POPA 5 POPAD POPAD 5 POPF POPF 6, PM = 4 POPFD POPFD 6, PM = 4
1.7, conversion command
XLAT [[segreg:] MEM] xlat 4 xlatb [[segreg:] MEM] xlatb ES: TABLE 4
1.8, input instruction
In Accum, IMMED IN AX, 60H 7, PM = 4, 21 * (Note), VM = 19 in Accum, DX IN AX, DX 7, PM = 4, 21 *, VM = 19 INS [ES:] DEST, DX INS ES: INSTR, DX 9, PM = 6, 24 *, VM = 22 INSB INSB 9, PM = 6, 24 *, VM = 22 INSW INSW 9, PM = 6, 24 *, VM = 22 INSD INSD 9 PM = 6, 24 *, vm = 22 Note: When CPL ≤ Iopl, execution time is the first clock cycle, otherwise it is a second clock cycle.
1.9, output instruction
OUT IMMED8, Accum Out 60H, Al 12, PM = 9, 26, VM = 24 OUT DX, Accum Out DX, AX 12, PM = 9, 25 VM = 24 OUTS DX, [Segreg:] SRC Outs DX, Buffer 13 , PM = 10, 27, VM = 24 OUTSB [DX, [segreg:] src] OUTSB 13, PM = 10, 27, VM = 24 OUTSW [DX, [Segreg:] SRC] OUTSW 13, PM = 10, 27 , VM = 24 OUTSD [DX, [segreg:] src] OUTSD 13, PM = 10, 27, VM = 24
2, logo bit operation instruction
2.1, logo bit operation instruction
Syntax Example Period CLC CLC 2 CMC CMC 2 STC 2 CLD 2 STD STD 2 CLI CLI 7 STI STI 7
2.2, logo bit access operation instruction
SAHF SAHF 2 lahf lahf 2
2.3, flag bit stack operation instruction
Pushf Pushf 4, PM = 3 Pushfd Pushfd 4, PM = 3 POPF POPF 6, PM = 4 POPFD POPFD 6, PM = 4
3, arithmetic operation instruction
3.1, addition instruction
The syntax of the instructions Period ADC REG, REG ADC DX, CX 1 ADC MEM, REG ADC WORD PTR M16 [2], DX 3 ADC REG, MEM ADC DX, DWORD PTR M32 [2] 2 Add Reg, REG ADD AX, BX 1 Add MEM, REG Add Total, CX 3 Add Reg, MEM ADD CX, INCR 2 Add MEM, IMMED ADD POINTERS [BX] [Si], 6 3 Add Acum, IMMED Add AX , 10 1 Inc Reg In BX 1 Inc MEM INC VPAGE 3 XADD REG, REG XADD DL, AL 3 XADD MEM, REG XADD STRING, BL 4
3.2, subtraction command
Sub Reg, Reg Sub AX, BX 1 Sub Mem, Reg Sub Array [Di], BI 3 Sub REG, MEM SUB AL, [BX] 2 Sub Reg, Immed Sub Bl, 7 1 Sub Mem, Immed Sub Total, 4000 3 Sub Acum, Immed Sub AX, 32000 1 SBB ACCUM, IMMED SBB AX, 320 1 SBB REG, IMMED SBB DX, 45 1 SBB MEM, IMMED SBB WORD PTR M32 [2], 40 3 SBB REG, REG SBB DX, CX 1 SBB MEM, REG SBB WORD PT M32 [2], DX 3 SBB REG, MEM SBB DX, WORD PTR M32 [2] 2 Dec REG AX 1 DEC MEM DEC Counter 3 NEG Reg Neg AX 1 Neg Mem Neg Balance 33.3, Multiplication instruction
Mul REG MUL BX MUL MUL MUL WORD PTR [BX] 8,16-bit = 11 32-bit = 10 Imul REG IMUL DX 11 Imul Memul Factor 11 Imul REG, IMMED IMUL CX, 25 10 Imul REG, REG, IMMED IMUL DX, AX, 18 10 Imul REG, MEM, IMMED IMUL BX, [SI], 60 10 Imul REG, REG IMUL CX, AX 10 Imul REG, MEM IMUL DX, [Si] 10
3.4, division instruction
Div Reg Div cx byte = 17 Word = 25 Div Mem Div [BX] DWORD = 41 IDIV REG IDIV DL 8-bit = 22; 16-bit = 30 IDIV MEM IDIV ITEMP 32-bit = 46
3.5, type conversion instruction
CBW CBW 3 CWD CWD 2 CWDE CWDE 3 CDQ CDQ 2
4, logical operation instruction
4.1, logic and operation instructions
The syntax of the instructions period is the number and reg, REG AND DX, BX 1 and MEM, REG AND BITMASK, BX 3 and reg, MEM AND BX, MASKER 2 and reg, IMMED AND DX, 0F7H 1 and mem, IMMED and MASKER, 100LB 3 and Accum, IMMED and AX, 0B6H 1
4.2, logic and operation instructions
OR REG, REG OR AX, DX 3 or REG, MEM OR DX, Color [DI] 2 or reg, immed or flag_rec, 8 3 or accum Immed OR AX, 40H 1
4.3, logic and operational instructions
NOT REG NOT AX 1 Not Mem Not Masker 3
4.4, logical varying or operating instructions
XOR REG, REG XOR CX, BX 1 Xor REG, MEM XOR CX, FLAGS 2 XOR MEM, REG XOR [BP 10], CX 3 XOR REG, IMMED XOR BL, 1 1 XOR MEM, IMMED XOR SWITCHES [BX], 101B 3 xor Accum, Immed XOR AX, 01010101B 1
, Shift operation instruction
5.1, arithmetic left shift instruction
The syntax of the instructions period Sal Reg, 1 Sal Bx, 1 1 Sal Mem, 1 Sal Word PTR M32 [0], 1 3 Sal REG, CL SAL AH, CL 4 Sal MEM, CL SAL BYTE PTR [DI], CL 4 Sal REG, IMMED SAL CX, 6 1 Sal Mem, Immed Sal Array [BX DI], 14 35.2, Right Movement
Sar Reg, 1 Sar Di, 1 1 SAR MEM, 1 SAR Count, 1 3 Sar Reg, Cl Sar BX, Cl 4 Sar Mem, Cl Sar Sign, Cl 4 Sar Reg, Immed Sar BX, 5 1 SAR MEM, IMMED SAR Sign_count, 3 3
5.3, logical left shift instruction
SHL REG, 1 SHL SI, 1 1 SHL MEM, 1 shl Index, 1 3 shl REG, CL SHL DI, CL 4 SHL MEM, CL SHL INDEX, CL 4 SHL REG, IMMED SHL DI, 2 1 SHL MEM, IMMED SHL Unsign, 4 3
5.4, logic right shift instruction
SHR REG, 1 SHR DH, 1 1 Shr MEM, 1 Shr unsign [di], 1 3 SHR REG, CL SHR DX, CL 4 SHR MEM, CL SHR WORD PTR M32 [2], CL 4 Shr REG, IMMED SHR BX , 8 1 Shr Mem, Immed SHR MEM16, 11 3
5.5, double precision left shift instruction
SHLD REG16, REG16, IMMED8 SHLD AX, DX, 10 4 SHLD REG32, REG32, IMMED8 SHLD MEM16, REG16, IMMED8 SHLD BITS, CX, 5 4 SHLD MEM32, REG32, IMMED8 SHLD REG16, REG16, CL SHLD AX, DX, CL 4 shld Reg32, Reg32, Cl SHLD MEM16, REG16, CL SHLD MASKER, AX, CL 5 SHLD MEM32, REG32, CL
5.6, double precision right shift instruction
Shrd Reg16, Reg16, Immed8 Shrd CX, Si, 3 4 Shrd Reg32, Reg32, Immed8 Shrd Mem16, Reg16, Immed8 SHRD [DI], DX, 5 4 Shrd Mem32, Reg32, IMMED8 Shrd Reg16, Reg16, Cl Shrd Ax, DX , CL 4 Shrd Reg32, Reg32, Cl Shrd Mem16, Reg16, Cl Shrd [BX], AX, CL 5 Shrd Mem32, Reg32, Cl
5.7, loop left shift instruction
The syntax of the instruction is a period of Rol REG, 1 ROL AX, 1 1 ROL MEM, 1 ROL BITS, 1 3 ROL REG, CL ROL AX, CL 4 ROL MEM, CL ROL Color, CL 4 ROL REG, IMMED8 ROL AX, 13 1 ROL MEM, IMMED8 ROL BYTE PTR [BX], 10 3
5.8, loop right shift instruction
Ror REG, 1 ROR AX, 1 1 ROR MEM, 1 ROR WORD PTR [BX], 1 3 ROR REG, CL ROR DX, CL 4 ROR MEM, CL ROR Color, Cl 5 ROR REG, IMMED8 ROR BL, 3 1 ROR MEM, Immed8 Ror Bits, 6 3
5.9, circulatory left shift instruction
RCL REG, 1 RCL DX, 1 1 RCL MEM, 1 RCL WORD PTR [Si], 1 3 RCL REG, CL RCL DX, CL 7-24 RCL MEM, CL RCL Masker, Cl 9-26 RCL REG, IMMED8 RCL BX , 5 8-25 RCL MEM, IMMED8 RCL WORD PTR [BP 8], 3 10-275.10, with the carrying loop right command
RCR REG, 1 RCR BL, 1 1 RCR MEM, 1 RCR WORD PTR M32 [0], 1 3 RCR REG, CL RCR BL, CL 7-24 RCR MEM, CL RCL Word PTR [BX = Di], CL 9- 26 RCR REG, IMMED8 RCR Si, 9 8-25 RCR MEM, IMMED8 RCR MASKER, 3 10-27
6, bit operation instruction
6.1, positive position scanning command
The syntax of the instruction is the number of syntax periods. BSF REG16, REG16 BSF CX, BX 6-34 BSF REG32, REG32 BSF CX, BX 6-42 BSF REG16, MEM16 BSF ECX, Bitmask 6-35 BSF REG32, MEM32 BSF ECX, Bitmask 6-43
6.2, positive position scan command
BSR Reg16, REG16 BSR CX, DX 7-39 BSR Reg32, Reg32 BSR ECX, EDX 7-71 BSR REG16, MEM16 BSR AX, Bitmask 7-40 BSR REG32, MEM32 BSR EAX, Bitmask 7-72
6.3, positive position scanning command
Bt REG16, IMMED8 * (Note) BT AX, 4 4 BT MEM16, IMMED8 BT [BX], 4 4 Bt Reg16, Reg16 BT AX, BX 4 BT MEM16, REG16 BT [BX], DX 9
(Note) The operand can also be a 32-bit number.
6.4, positive position scanning command
BTC Reg16, IMMED8 * BTC EDI, 4 7 BTC MEM16, IMMED8 * BTC Color [Di], 4 8 BTC REG16, REG16 * BTC EAX, EBX 7 BTC MEM16, Reg16 * BTC [BP 8], Si 13
6.5, positive position scanning instruction
Btr REG16, IMMED8 * BTR BX, 17 7 BTR MEM16, IMMED8 * BTR [BX], 27 8 BTR REG16, Reg16 * BTR CX, DI 7 BTR MEM16, Reg16 * BTR Rotate, CX 13
6.6, positive position scanning instruction
BTS Reg16, IMMED8 * BTS AX, 4 7 BTS MEM16, IMMED8 * BTS Maskit, 4 8 BTS Reg16, Reg16 * BTS BX, AX 7 BTS MEM16, REG16 * BTS FLAGS [BX], CX 13
6.7, positive position scanning command
Test Reg, Reg Test DX, BX 1 Test Mem, Reg Test Flags, DX 2 Test Reg, Immed Test CX, 30H 1 Test Mem, Immed Test Masker, 1 2 Test Accum, Immed Test AX, 90H 1
7, comparative operation instruction
7.1, compare instructions
The syntax of the instructions Period CMP REG, REG CMP DL, CL 1 CMP MEM, REG CMP Array [Si], BL 2 CMP REG, MEM CMP BH, ARRAY [Si] 2 CMP REG, IMMED CMP BX, 24 1 CMP MEM Immed CMP Tester, 4000 2 CMP Accum, IMMED CMP AX, 1000 1
7.2, compare exchange instructions
CMPXCHG MEM, REG CMPXCHG STRING, BL 6 CMPXCHG REG, REG CMPXCHG BX, CX 6 CMPXCHG8B REG, MEM64 CMPXCHG8B AX, [BX] 108, Cyclic Directive
8.1, loop instruction
Loop Label Loop Wend 5, 6 Loope Label Loope Again 7, 8 Loopz Label Loopz Again 7, 8 Loopne Label Loopne For_Next 7, 8 Loopnz Label Loopnz for_Next 7, 8
8.2, loop instruction
JCXZ Label Jcxz Notfound 6, 5 Jecxz Label Jecxz Notfound 6, 5
9, transfer instruction
9.1, unconditional transfer instruction
The syntax of the instructions period JMP label Jmp Near PTR Distant 1 JMP Distant 3 JMP REG16 JMP AX 2 JMP MEM16 JMP Table [Di] 2 JMP REG32 JMP EAX 3 JMP MEM32 JMP FPOINTER [Si] 2 JMP MEM48 JMP FWORD PTR [DI] 4
9.2, condition transfer instruction
JCONDITION Label Je Next 1
9.3, subroutine call instruction
Call Label Call Upcase 1 Call Distant 4 Call Reg Call AX 2 Call Mem32 Call [BX] 2 Call Mem32 Call Dword PTR [BX] 5
9.4, subroutine return instruction
Retn Retn 2 Retn IMMED16 RETN 8 3 RETF RETF 4, 23 RETF IMMED16 RETF 32 4, 23
9.5, interrupt command
INT IMMED8 INT 25H 16, PM = 31, 48 * (Note) INT 3 INT 3 13, PM = 27, 44 * INTO INTO 13, PM = 27, 44 *
Note: The first time is an interruption time of the same priority, and the second time is high priority interrupt time.
9.6, interrupt return instruction
IRET IRET 8 * (Note), 10, PM = 27 IRETD IRETD 10, PM = 27 IRETF IRETF IRETDF IRETDF
Note: Real aspect or virtual 8086 mode.
10, condition setting byte instruction
SetCondition Reg8 setc DH 1 setCondition MEM8 SETLE FLAG 2
11, string operation instruction
11.1, string data instruction
The syntax of the instructions is the number of cycles of the period. LODS [segreg:] src lods es: source 2 lodsb [[segreg:] src] lodsb 2 lodsw [[segreg:] src] lodsw 2 lodsd [[segreg:] src] Lodsd 2
11.2, set string data instructions
Stor es: dstring 3 stosb [[es:] dest] Stosb 3 stosw [[es:] de: Stosw 3 stosd [[es:] dest] Stosd 3
11.3, string transmitting instruction
Movs [ES:] DEST, [Segreg:] SRC MOVS DEST, ES: Source 4 MOVSB [[ES:] DEST, [Segreg:] SRC] Movsb 4 Movsw [[ES:] dest, [segreg:] src] MOVSW 4 movsd [[es:] dest, [segreg:] src] MOVSD 4
11.4, enter string instructions
INS [ES:] DEST, DX INS ES: INSTR, DX 9, PM = 6, 24 *, VM = 22 INSB INSB 9, PM = 6, 24 *, VM = 22 INSW INSW 9, PM = 6, 24 * , VM = 22 INSD INSD 9, PM = 6, 24 *, VM = 2211.5, output string command
OUTS DX, [Segreg:] SRC OUTS DX, Buffer 13, PM = 10, 27, VM = 24 OUTSB [DX, [Segreg:] SRC] OUTSB 13, PM = 10, 27, VM = 24 OUTSW [DX, [ Segreg:] SRC] OUTSW 13, PM = 10, 27, VM = 24 OUTSD [DX, [Segreg:] SRC] OUTSD 13, PM = 10, 27, VM = 24
11.6, string comparison instruction
CMPS [Segreg:] SRC, [ES:] DEST CMPS SOURCE, ES: DEST 5 CMPSB [[SegReg: [src,] es:] de: [src,] es:] de) cmpsw 5 cmpsd [[Segreg: [src,] es:] dest] CMPSD 5
11.7, string scan instruction
SCAS [ES]: DEST SCAS ES: Destin 4 ScaSB ScaSB 4 ScASW ScASW 4 SCASD 4
11.8, repeat prefix command
REP INS DEST, DX REP INS DEST, DX 11 3N, PM = (8, 25) 3N * REP MOVS DEST, SRC REP MOVS DEST, SOURCE 6, 13N Rep Outs DX, SRC Rep Outs DX, Source 13 4N , PM = (10, 27) 4N * REP LODS DEST REP LODS DEST 7, 7 3N Rep Stos Dest Rep Stos DEST 6, 9 3N
Note: When CPL ≤ Iopl, execution time is the first clock cycle, otherwise it is the second clock cycle.
11.9, equal repeat prefix command
REPE CMPS SRC, DEST REPE CMPS SRC, DEST 7, 9 4N REPE SCAS DEST REPE SCAS DEST 7, 9 4N
11.10, non-equal repeat prefix instruction
Repne CMPS SRC, DEST RepNE CMPS SRC, DEST 7, 8 4N Repne Scas Dest Repne Scas DEST 7, 9 4N
12, ASCII-BCD code operation adjustment instruction
The syntax of the instructions Period AAA AAA 3 AAD AAD 10 AAM AAM 18 AAS AAS 3 DAA DAA 3 DAS DAS 3
13, processor instruction
HLT HLT 12 NOP NOP 1 WAIT WAIT 1 LOCK LOCK 1
14, coprocessor directive
