GNU Make and Makefile
GNU Make Makefile Basic Structure Makefile Variable GNU Make's main predefined variable implicit rules makefile example Run MAKE
1.9.1 GNU Make
In large development projects, there are usually dozens to hundreds of source files. If you are manually type a GCC command, it will be very inconvenient. Therefore, people usually use the MAKE tool to automatically complete the compilation. These tasks include: If only a few source files are modified, only these source files are recompiled; if a header file is modified, you recompile all the source files that contain the header file. This automatic compilation can greatly simplify development efforts to avoid unnecessary recompilation. In fact, the Make tool completes and automatically maintains compilation through a file called Makefile. Makefile needs to be written in a syntax, which describes how to compile individual source files and connect to generate executables, and define dependencies between source files. When a source file is modified, if other source files rely on this file, you should also recompile all source files that depend on the file. The Makefile file is a lot of compilers, including compilers under Windows NT Maintaining Common Method for Compile Information, just modifying the Makefile file through the friendly interface in an integrated development environment. By default, GNU Make Tools Search Makefile in the current working directory: * Gnumakefile * makefile * makefile in the UNIX system, is used to using makefile as a Makfile file. If you want to use other files as makefile, you can specify your Makefile file similar to the following MAKE command: $ make -f makefile.debug
1.9.2 Makefile Basic Structure
Makefile generally includes the following: * Items that need to be created by the Make tool, usually the target file and executable. Usually use the word "target" to indicate the item to be created. * What files are dependent on items to be created. * The command that needs to be run when you create each item. For example, suppose you now have a C source file Test.c, which contains a custom header file Test.h, the target file Test.o explicitly depends on two source files: Test.c and Test.h.h. In addition, you may only want to use the G command to generate a Test.o target file. At this time, you can use the following makefile to define Test.o creation rules:
# This makefile just is a example. # # Test.o Depends # test.c and test.h, and how to create test.o
Test.o: Test.c Test.hg -c -g test.c
From the above example notes, the first character is a # 行 注 行 行 行. The first non-promised line specifies Test.o as a target and rely on Test.c and Test.h files. The subsequent line specifies how to establish a goal from the files dependent on the target. When Test.c or test.h file is modified after compiling, the Make tool can automatically recompile Test.o. If the two compilations are compiled before and after, Test.c and Test.h have not been modified, and Test If still exists, there is no need to recompile. This dependency is especially important in program compilation of multi-source files. With this definition of this dependency, the Make tool avoids many unnecessary compilation work. Of course, using the shell script can also reach the automatic compilation effect, but the shell script will all compile any source files, including which unnecessary recompiles, and the Make tool can be based on the time and target of the target last time and target The update time of the source file is automatically determined which source file should be compiled. A MakeFile file can define multiple targets, using the make target command to specify the target to be compiled, if the target is not specified, use the first target. Typically, the makefile defines a Clean target, which can be used to clear an intermediate file during the compilation process, such as: Clean: RM -F *. When running make clean, the RM -F * .O command will be executed, and finally delete all compilation processes. All intermediate files generated. 1.9.3 Makefile variable
In addition to providing basic functions with the establishment of the goals, the GNU's Make tool has many features that express dependence relationships and commands to establish targets. One of them is the definition of variables or macros. If you want to compile more than a dozen C source files at the same time, you will be very tedious for each target's compilation. But using simple variables definition to avoid this boring job:
# Define macros for name of compilercc = GCC
# Define a macr o for the cc flagsccflags = -d_debug -g -m486
# A rule for building a object filetest.o: Test.c Test.h $ (cc) -c $ (ccflags) Test.c
In the above example, CC and CCFLAGS are MAKE variables. GNU Make is usually called a variable, while other UNIX's Make tools are called macros, it is actually the same thing. When the value of the variable is referenced in the makefile, you only add $ symbols before the variable name, such as $ (cc) and $ (ccflags) above.
1.9.4 GNU Make's main predefined variable
GNU Make has many predefined variables that have special meanings and can be used in rules. Table 1-5 shows some main predefined variables, in addition to these variables, GNU Make also uses all environment variables as their predefined variables.
Table 1-5 The main predefined variable of GNU Make predefined variables $ * does not include the target file name of the extension. $ All dependencies, separated by spaces, and preface, may contain duplicate dependencies. $ GNU Make contains a number of built-in or implicit rules that define how to establish specific types of targets from different dependent files. GNU Make supports two types of implicit rules: * Suffix rules. Suffix rules are old-style methods that define hidden rules. The suffix rule defines a method of converting a file (for example, .c file) with a suffix to a file (eg, .o file) having another suffix. Each suffix rule is defined in two vectors, for example, the suffix rule converts the .C file to .o files can be defined: .C.O: $ (CC) $ (cppflags) -c-@ @ $ < * Pattern Rules. This rule is more common because it can be used to define a more complex dependency rules using the mode rule. Mode rules look very similar to regular rules, but there are more than one% in front of the target name, and can be used to define relationships between targets and dependencies. For example, the following mode rules define how to convert any of the XC files to XO file: % .c:%. O $ (cc) $ (cppflags) -c-@ @ $ @ 1.9.6 Makefile Example 1.9.7 Run Make We know that the target name can be established directly after the Make command, and if you run Make directly, the first goal is established. We also know that Make can specify make -f mymakefile to specify make using specific makefile, not the default gnumakefile, makefile, or makefile. However, there are some other options in the gnu board command, and these options are given. Table 1-6 General command line options for gnu board commands
