GNU Make and Makefile
GNU Make Makefile Basic Structure Makefile Variable GNU Make's main predefined variable implicit rules makefile example Run MAKE
1.9.1 GNU Make
In large development projects, there are usually dozens to hundreds of source files. If you are manually type a GCC command, it will
very inconvenient. Therefore, people usually use the MAKE tool to automatically complete the compilation. These tasks include: If only a few
Source files, only to recompile these source files; if a header file is modified, all source files that contain the header file are recompiled.
This automatic compilation can greatly simplify development efforts to avoid unnecessary recompilation.
In fact, the Make tool completes and automatically maintains compilation through a file called Makefile. Makefile needs to follow some
The syntax is written, which describes how to compile individual source files and connect to generate executables, and define dependencies between source files.
When a source file is modified, if other source files rely on this file, you should also recompile all source files that depend on the file.
Makefile file is a many compiler, including compilers under Windows NT Maintaining Common Methods for Compile Information, just in integrated development
In the territory, users modify the Makefile file through the friendly interface.
By default, GNU Make Tools Search Makefile in the order in the current working directory:
* Gnumakefile
* Makefile
* Makefile
In UNIX systems, use Makefile as a Makfile file. If you want to use other files as Makefile, you can use the class.
Specify the makefile file as the Make command option below:
$ Make -f Makefile.debug
1.9.2 Makefile Basic Structure
Makefile usually contains the following:
* Items that need to be created by the make tool, usually the target file and executable. Usually use the word "target"
Items to create.
* What files are dependent on items to be created.
* The command that needs to be run when you create each item.
For example, suppose you now have a C source file Test.c, the source file contains a custom header file Test.h, the target file Test.o
Depending on the two source files: Test.c and Test.h. In addition, you may only want to use the G command to generate a Test.o target file.
At this time, you can use the following makefile to define Test.o creation rules:
# This makefile Just is a example.
# The folowing lines indicate how test.o dependeed
# Test.c and test.h, and how to create test.o
Test.o: test.c test.h
G -c -g test.c
From the above example notes, the first character is a # 行 注 行 行 行. The first non-invasive line specified Test.O is the target, and dependent on
Test.c and test.h files. The subsequent line specifies how to establish a goal from the files dependent on the target.
When Test.c or Test.h file is modified after compiling, the Make tool can automatically recompile Test.o, if it is two times before and after
Between compilation, Test.c and Test.h have not been modified, and Test.o still exists, there is no need to recompile. This dependency is especially important in program compilation of multi-source files. With this dependency definition, the Make tool avoids many unnecessary compilers.
Work. Of course, using the shell script can also reach the automatic compilation effect, but the shell script will all compile any source files, including
What don't need to recompile the source file, while the Make tool can be updated according to the time of the target and the source file rendered by the target.
Time and automatic judgment should be compiled which source file.
A Makefile file can define multiple targets, using the make target command to specify the target to be compiled, if you do not specify the target,
Use the first goal. Typically, the makefile defines a Clean target, which can be used to clear intermediate files during the compilation process, for example:
Clean:
RM -F * .O
When running make clean, the RM -F * .O command will be executed, and finally delete all the intermediate files generated during all compilation processes.
1.9.3 Makefile variable
In addition to providing basic functions of establishing goals, GNU's Make tools, there are many expressions that are easy to express dependence relationships and to establish targets.
color. One of them is the definition of variables or macros. If you want to compile more than dozens of C source files at the same time, for each purpose
The target compiles to specify the lengthy compile option, it will be very bored. But using simple variables definition to avoid this boring job:
# Define Macros for Name of Compiler
CC = GCC
# Define a macr o for the cc flags
Ccflags = -d_debug -g -m486
# A rule for building a object file
Test.o: test.c test.h
$ (Cc) -c $ (ccflags) Test.c
In the above example, CC and CCFLAGS are MAKE variables. GNU Make is usually called variables, while other UNIX MAKE
The tool is called the macro, it is actually the same thing. When references the value of the variable in makefile, you only add $ symbol before the variable name, such as
$ (CC) and $ (ccflags) above.
1.9.4 GNU Make's main predefined variable
GNU Make has many predefined variables that have special meanings and can be used in rules. Table 1-5 shows some main
Predefined variables, in addition to these variables, GNU Make also uses all environment variables as their predefined variables.
Table 1-5 Main predefined variables for GNU Make
Predefined variable meaning
$ * Does not contain the target file name of the extension.
$ All dependencies, separated by spaces, and preface, may contain duplicate dependencies.
$ $? All dependencies, separated by space, the modification date of these dependencies is late than the creating date of the target. $ @ 目 目 's full name. $ ^ All dependencies, separated by space, does not contain duplicate dependencies. $% If the target is an archive member, the variable indicates the name of the target's archive member. For example, if the target name For MyTarget.so, $ @ is MyTarget.so, and $% is image.o. The name of the AR archive maintenance program, the default value is Ar. Arflags Archive Maintenance Options. The name of the AS assembler, the default value is as. Asflags assembler options. The name of the CC C compiler, the default value is CC. The CCFlags C compiler options. The name of the CPP C precompiler is $ (cc) -e. CPPFLAGS C precompiled options. The name of the CXX C compiler, the default value is G . CXXFLAGS C compiler options. The name of the FC Fortran compiler, the default value is F77. FFlags Fortran compiler options. 1.9.5 implicit rules GNU Make contains a number of built-in or implicit rules that define how to establish specific types of targets from different dependent files. GNU Make supports two types of implicit rules: * Suffix rules. Suffix rules are old-style methods that define hidden rules. Suffix rules define a one with a certain The suffix file (for example, .c file) is converted to a method with another suffix file (eg, .o file). Each suffix ruler The suffix rule that converts the .C file to .o file with two pairs, the suffix rule converted to .o files can be defined as: .c.o: $ (Cc) $ (ccflags) $ (cppflags) -c-@ @ $ < * Pattern Rules. This rule is more common because it can be used to define a more complex dependency rules using the mode rule. Mode rules look very similar to regular rules, but there are more than one% in front of the target name, and can be used to define targets and dependencies. The relationship between files, such as the following mode rules define how to convert any one X.c file to the X.O file: % .c:%. O $ (Cc) $ (ccflags) $ (cppflags) -c-@ @ $ < 1.9.6 Makefile Example 1.9.7 Run Make We know that the target name can be established directly after the Make command, and if you run Make directly, aims. We also know that Make can specify make -f mymakefile to specify make use a specific makefile, not Default gnumakefile, makefile or makefile. However, there are some other options in the gnu board command, and Table 1-6 is given. These options. Table 1-6 General command line options for gnu board commands Command line option meaning -C Dir changes to the specified directory DIR before reading Makefile. -f file as the specified File file as a makefile. -H Displays all Make options. -i ignores all command execution errors. -I DIR When containing other Makefile files, you can specify the search directory using this option. -n only prints the command to be executed, but these commands are not executed. -p Displays the MAKE variable database and implicit rules. -s Do not display the command when executing the command. -w The working directory is displayed before and after processing makefile. -W file assumes that the file file has been modified.
