I. Data transfer instructions - ─────────────────────────────── ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ Data between registers, registers, and input / output ports. Push the word pile. Pusha pressed the AX, CX, DX, BX, SP, BP, SI, DI in the stack. Popa pops up DI, Si, BP, SP, BX, DX, CX, AX, pops up the stack. Pushhad EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI sequentially press the stack. Popad pops EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX pops up the stack. BSWAP swaps the byte of the 32-bit register Sequentially XCHG exchange word or bytes. (At least one operand is the register, the segment register is not operated as an operand) CmpxCHG compares and exchanges the operand. (The second operator must be accumulator Al / Ax / eax) XADD first exchange Recumet. (Results in the first operation) XLAT byte check table conversion. ─ BX point to the starting point of a 256-byte table, Al is the index value of the table (0-255, 0-FFH) Returns Al is the results of the surfaction table. ([BX Al] -> Al) 2. Enter the output port transfer command. In I / O port input. (Syntax: in accumulator, {port number │DX}) OUT I / O port output. (Syntax: OUT {port number │DX}, accumulator) The input output port is specified by the immediate way, and its range is 0-255; when the register DX is specified, its range is 0-65535. 3. Purpose Address Transfer Directions. Example: Lea DX, String; Departing the offset address to DX. LDS transmission target pointer, put the pointer content into DS. Example: LDS Si, String; Put the segment address: Offset The address exists to the DS: Si. LES Transmit the target pointer, put the pointer content into the ES. Example: les di, string; put the segment address: Offset Address to ES: Di. LFS Transfer Target Pointer, put the pointer content into FS Example: LFS Di, String; Deploying Segment Address: The Offset Address to FS: DI. LGS Transfer Target Pointer, put the pointer content into GS. Example: LGS Di, String; put the segment address: Offset address to GS : Di. LSS transmits the target pointer, put the pointer content Loading SS. Example: LSS Di, String; Deposit Segment Address: Offset Address to SS: DI. 4. Sign Transfer Instruction. Lahf Sign Register Transfer, put the flag into ah. Sahf flag register, put ah content Into the logo register. Pushf flag is in the stack. PUSHD 32-bit flag enables the stack. Second, arithmetic operation instructions --- - ─────────────────────────────────── ──────────────── ADD addex method. Inc plus 1. AAA addition ASCII code adjustment. DAA additive decision. SUB subtraction SBB with borrowing subtraction. Decimal 1. NEC to reverse (decreased by 0). CMP comparison. (Two Operations subtracted, only modify the flag, no return result). AAS subtssion ASCIII code adjustment. DAS subtssion The decimal adjustment. MUL unsigned multiplication. IMUL integer multiplication. The above two, the results are returned to AH and Al (byte operation), or the AAM multiplication ASCII code adjustment. DIV unsigned division. Idiv Integer division. The above two, the result is sent to: the merchant sent Al, the remainder will return AH, (byte operation); or the rest of the AX, (word operation). AAD division ASCII code adjustment. CBW byte converted to Word. (Extend the symbol of the AL to AH) CWD word to double words. (Extended the symbols in the AX to DX) CWDE word to double words. (Put the characters in AX). Extended to EAX to) CDQ double word extension. (Extended the symbols in Eax to EDX)
Third, logical operations - ─────────────────────────────── And and calculation. OR or or Operation. Xor is too or calculation. NOT reflects. Test test. (Two Operations, only modify flag bits, no return results). SHL logic left shift. SAL arithmetic left shift. (= SHL) SHR logic right shift . SAR algorithography right shift. (= SHR) ROL loop left shift. RC loop right shift. RCL is moved left by the RCR. RCR is shifted by the RCR. The above eight shift instructions, the number of shifts can be up to 255 Time. When you shift once, you can use the operation code directly. Such as SHL AX, 1. Shift> 1 time, the number of shifts is given by the register CL. Such as MOV CL, 04 SHL AX, CL 4, string instructions- ───────────────────────────── DS: Si source segment register: Source string ES: Di Target Series Segment Register: Target String Litter. CX Repeated Double Number. AX Scan Value. D Sign 0 indicates that Si and Di should be automatically incremented in repeated operation; 1 indicates automatic reduction. Z mark To control the end of the scan or comparison operation. MOVS string transfer. (Movsb transfer character. MovsW transmission word.) CMPS string comparison. (CMPSB comparison characters. CMPSW comparison word.) ScaS String scan. Put Al or AX The content is compared with the target string, and the comparison results are reflected in the flag. LODS is loaded. Put the elements (words or bytes in the source string) in Al or AX one by one. (LODSB Transfer Character. Lodsw Transportation word. Lodsd Transfer double word.) STOS save string. Is the reverse process of the LODS. REP is repeated when CX / ECX <> 0. REPE / REPZ is equal to ZF = 1 or the comparison result, and CX / ECX <> 0 is repeated. Repne / REPNZ is repeated when ZF = 0 or comparison results is not equal, and CX / ECX <> 0 is repeated. REPC is repeated when CF = 1 and CX / ECX <> 0. REPNC is repeated when CF = 0 and CX / ECX <> 0 .
Five, the program branch instruction ─────────────────────────────────────── 1> unconditional jump instruction ( Chang transfer) JMP unconditional transfer command CALL process call RET / RETF process returns. 2> Condition transfer command (short transfer, -128 to 127) (when and only when (sf xor of) = 1, OP1 < OP2) JA / JNBE is not less than or not equal to time transfer. JAE / JNB is greater than or equal to transfer. JB / JNAE is less than transfer. JBE / JNA is less than or equal to transfer. The above four, test unsigned integer operations (Sign C and Z ). JG / JNLE is greater than the transfer. JGE / JNL is greater than or equal to the transfer. JL / JNG is less than the transfer. JLE / JNG is less than or equal to the transfer. The above four, the results of the test band symbol integer operation (flag S, O and Z). JE / Jz is equal to the transfer. JNE / JNZ is not equal to the time transfer. The JC is transferred. JNC is transferred. JNO does not overflow. JNP / JPO parity is odd. The JNS symbol bit is "0" time transfer. . JO overflow transition. JP / JPE parity is a transfer. The JS symbol bit is transferred when the JS symbol bit is "1". 3> Cycle control command (short transfer) Loop CX is not zero cycle. Loope / Loopz CX is not zero Sign Z = 1 Time cycle. Loopne / loopnz CX is not zero and log z = 0 cycles. JCXZ CX is zero transfer. JECXZ ECX is zero transfer. 4> Interrupt command int interrupt instruction INTO overflow interrupt IRET interrupt Return 5 > Processor Control Communication The HLT processor is paused until an interrupt or reset signal will continue. Wait When the chip lead Test is high-speed timing, the CPU enters the waiting state. ESC is converted to the external processor. Lock blockbus bus. NOP air operation. STC. Enter the entered sign bit. CLC inlet marker. CMC carry flag reflects. STD direction flag. CLD clearance flag. STI set interrupt allow bit. CLI clear interrupt allowed bit. Six, pseudo instructions --- ────────────────────────── DW definition word (2 bytes). PROC definition process. Endp process end Segment definition segment. Assume settles segment register addressing. Ends end. End program ends.
