The command to create a package provided by the GNU organization is when the make command. When executing make, it automatically looks for Makefile or makefile files and performs the creation process in which definitions. The Makefile file supports the syntax of the shell programming, consisting of a set of rules that creates a package, the format of the rules is as follows: target: dependency defendency [...] command command [...] target indicates the target of the make command to perform. Dependency indicates that the object that needs to be dependent when performing this target, and multiple dependent objects are spaced apart. Command indicates the command used when performing the target, and multiple Commans are used multiplexed. It should be noted that there must be 8 characters of spaces before the Command line, which is the length of a Tab key. Otherwise, makefile files are often considered to be damaged and cannot be used. Write the usual method of Makefile: 1. Defining variable definition variables allows the Makefile file to look more concise and specified, and the definition of variables follows the shell programming specification. For example: cc = g c = GCC definitions a source file variable: Sources = main.cpp precompile.cpp If you want to go down in the end, then add a backslash "/", such as: Sourcees = Main.cpp / precompile.cpp 2. Define Creating Rules When you need a variable, you can form a complete makefile file in accordance with the format of the creating rules. For example: $ {Objects}: $ {sources} $ (incrudes) $ {sources} This rule means: To create $ {Objects}, not only relying on $ {sources}, To execute command $ (cc) -c $ (cflags) $ (incrudes) $ {sources}, $ (xx) in this rule represents the variable we just defined.
Here is a simple instance to tell how to make a makefile, I will use the comment (#) to explain.
# Define the command name variable of the compiler. CC = G
# Define the compiler option variable. Cflags = -g
# Define the incline file or folder variable, # - i represents the actual content of the include option, and after the -i. INCLUDES = -i. -I / usr / lib
# Define the library file or folder variable. Libs = -L.
# Define Output File Name PRG = Testit
# Define the source file list variable, multiple file security directly using spaces. Sources = main.cpp / precompile.cpp
# Define the target file list variable, multiple file security directly using spaces, the order of the # file is consistent with the definition Sources variable. Objects = main.o / precompile.o # Rule All, which depends on the $ {prg} rule without executing a command. All: $ {prg}
# 规 规 {prg}, it depends on the $ {Objects} rule, # and executes commands to connect the target file to the program file. $ {Prg}: $ {{} -o $ {prg} $ {Objects} $ {libs} # rule $ {Objects}, depending on $ {sourcees} variable, # and execute the source file compilation Command to the target file. $ {Objects}: $ {sources} $ (cflags) $ (incrudes) $ {sources} # rule clean, it does not rely on other rules, # executes forcibly emptying target files and core dump files command. Clean: RM -F $ {Objects} Core
It's not difficult, I believe that by some exercises, you will definitely write better Makefile files.
You can also try automatically generating makefile tools, such as AutoScan, AutoConf, Automark, etc., the following is a very good article: http://vindaci.members.sonic.net/cbreak/projects/autotools/index.php3
