Exception: An event caused by internal / external sources requires a processor intervention, each exception mode has its own special function register, stack. Treatment exception requires the current state of the processor to resume execution after abnormality processing. When an abnormality occurs, the system enforces the executor from the fixed address.
When entering anomalies, PC-> R14 and CPSR-> SPSR hold PC and processor status, return, CPSR-> SPSR, R14-> PC.
Interrupt is a subset of abnormalities. Uninterrupted usually points to an empty function. The ARM provides two interrupt sources IRQ, FIQ. When an interrupt occurs, the corresponding IRQ, FIQ exception mode is interrupted, and different interrupts are identified by the exception handler, call the corresponding interrupt service program.
ARM's abnormal vector table position: starting from the 0x0 address, the space for 8 × 4 bytes of space, specific allocation:
Handlereset # 4 Handleundef # 4 Handleswi # 4 HandlePrefetch # 4 HandlereAbort # 4 HandlereServ # 4 Handleirq # 4 Handlefiq # 4
VxWorks processes: Store the corresponding exception handler pointer (or address) at the memory 0x100, store the PC pointer loading instruction, LDR PC, [PC, # 100] in 0x0, to add 0x100 abnormality Processing function.
VxWorks for ARM uses only IRQ exceptions, all external interrupt ISRs are in portions with IRQ exception handling routines. When an external interrupt causes an IRQ exception, the IRQ exception handling routine calls the ISR in the interrupt vector table.
Interrupt nesting: General, VxWorks uses interrupts in a non-reinforced manner, defined in config.h: #DEFINE INT_MODE INT_NON_PREEMPT_MODEL
When using reusable interrupt mode, there is interrupt nested, you need to save the stack and return address. (SVC protection mode).
Detail ...
MMU: MMU is an abbreviation for the memory management unit, is a device used to manage a virtual memory system. The MMU is usually part of the CPU, which has a small amount of storage space to store a matching table from the virtual address to the physical address. This table is called TLB (converted a side buffer). All data requests are sent to the MMU, and the data is determined by the MMU whether it is within the RAM or within a large capacity memory device. If the data is not in the storage space, the MMU will generate a page error interrupt.
Generally, using MMU solves the following problems:
1 When using DRAM as a large-capacity memory, if the row of DRAMs is non-squarete, it will cause the physical address of the DRAM to be discontinuous, which will give the program to write debugging, and properly configure the MMU to convert it into a virtual address Continuous space.
The interrupt vector table of the 2ARM kernel requires the 0 address, for the case where the ROM is 0 address, the interrupt service program cannot be debugged, so it is necessary to map the readable memory space to the 0 address during the debug phase.
3 Some address sections of the system are not allowed to be accessed, otherwise it will produce unpredictable consequences, in order to avoid such errors, these address segments can be set to the user's inequential type.
In IXP1200, the physical address 0-24m of SDRAM is supplied to the microcode, and the physical address 0x1800000 is mapped to the virtual address 0x0.
Note: After the MMU is enabled, the program continues to run, the program counter pointer has changed, pointing to the corresponding virtual address, pay attention to the debugging.
