Inter-Integrated Circuit
The bus is a two-wire serial developed by Philips.
The bus is used to connect the microcontroller and its peripherals.
I2C
The bus is generated in the 1980s, initially developed for audio and video equipment, now mainly used in server management, including communication of a single component state. For example, an administrator can query each component to manage the configuration of the system or mastery of components, such as power and system fans. You can monitor multiple parameters such as memory, hard disk, network, and system temperature at any time, adding the security of the system, which is convenient for management.
1
I2C
Bus characteristics
I2C
The main advantage of the bus is its simplicity and effectiveness. Since the interface is directly above the components,
I2C
The bus occupation is very small, reducing the number of spaces of the board and the number of chip pin, which reduces the interconnection cost.
The bus length can be as high as 25 feet and 40 components can be supported at the maximum transmission rate of 10 kbps.
I2C
Another advantage of the bus is that it supports multimastering, with any devices capable of transmitting and receiving them into the master.
bus. A master can control the transmission and clock frequency of the signal. Of course, there can only be a master at any point in time.
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I2C
Bus working principle
2.1
Composition and signal type
I2C
The bus is a serial consisting of data line SDA and clock SCL
Bus, can send and receive data. Between the CPU and the Control IC, the IC is bidirectional between the IC, and the maximum transfer rate is 100Kbps. All kinds of
Control circuit is connected in parallel
Online, but just like a telephone only to work, each circuit and module have a unique address, during the transmission of information,
I2C
Each module circuit on the bus is both a master (or a controller), and the transmitter (or receiver), depending on the function therebetween. The control signals issued by the CPU are divided into two parts: address code and control, i.e., the circuit that needs to be controlled, determines the type of control; the control amount determines the category of the adjustment (such as contrast, brightness, etc.) and Need to adjust the amount. In this way, each
Although the control circuit is hung in the same
On the bus, it is independent of each other and is not related to each other.
I2C
The bus has three types of signals during transmission data, which are: start signal, end signal, and response signal.
Start signal: When SCL is high, SDA is hopped by a high level to low level and start transmitting data.
End Signal: When SCL is low, SDA is hopped by a low level to a high level and end transmitting data.
Answer signal: After receiving the data of the data, after receiving the 8bit data, the IC of the transmitted data issues a specific low level pulse, indicating that the data has been received. After the CPU issues a signal to the controlled unit, the CPU waits for a response signal to wait for a response signal, and the CPU is received, and the determination of whether to continue the signal is proceeds according to the actual situation. If the response signal is not received, it is faulty by judging the controlled unit.
There are currently many semiconductor integrated circuits to integrate
I2C interface. Have
The microcontrollers of the I2C interface include: Cygnal's C8051F0XX series, philipsp87lpc7xx series, Microchip's PIC16C6XX series, etc. Many peripherals such as memory, monitoring chips, etc.
I2C interface.
3
Bus basic operation
The I2C procedure uses the master / from two-way communication. Device sends data to
On the bus, it is defined as a transmitter, and the device receives data is defined as a receiver. The master and slave devices can be operated in receiving and transmitting.
The bus must be controlled by the master (usually microcontroller), the main device generates a serial clock (SCL) control bus transmission direction and generates start and stop conditions. The data state on the SDA line can only change in the period of the SCL to a low level, and the SCL is the high level, and the change in the SDA state is used to indicate the start and stop conditions. See Figure 1.
3.1 Control bytes
After starting conditions, it must be the control byte of the device, where the high four bits are the device type identifier (different chip types have different definitions, EEPROM should generally be 1010), then three is the chip select, the last one For the readout, when 1 is 1, it is 0, and is 0. as shown in picture 2.
3.2 Write operation
Write operation is divided into two operations from byte writing and page, which is different from the one-loaded byte of the chip. See Figure 3 about the timing of the address, response, and data transfer of the page.
3.3 read operation
There are three basic operations: current address read, random read and sequential read. Figure 4 shows a timing chart for sequential reading. It should be noted that the nine clock cycle of the last read operation is not "not care". In order to end the read operation, the host must issue a stop condition during the 9th week or maintain SDA at a high level within the 9th clock cycle, and then stop condition.
4 examples: Implementation of X24C04 and MCS-51 single-chip microcomputer
X24C04 is a CMOS 4096-bit serial EEPROM of Xicor, an internal organized 512 × 8 bits. The 16-byte page is written. The MCS-51 single-chip interface is shown in Figure 5. Since SDA is a drain open output, and can be connected to any number of drain open or a Wire-ORED connection. The selection of the pull-up resistor can refer to the data sheet of X24C04. Below is through
The I2C interface performs a single-byte write operation for X24C04. The flow chart and source procedures are as follows:
; Name: bsent
Description: Writing bytes
Function: Write a byte
; Calling program: no
; Input parameters: a
Output parameters: no
BSEND: MOV R2, # 08h; 1 byte 8
Senda: CLR P3.2;
RLC A; left shift one
MOV P3.3, C; write one
Setb P3.2
DJNZ R2, Senda; write 8 bytes?
CLR P3.2; Response signal
Setb P3.3
Setb P3.2
RET
5 Conclusion
in
I2C
The matters that should be noted in the bus application are summarized as follows:
1) Operation in strict accordance with the requirements of the timing map,
2) If the single-chip interface is connected to the internal pull-up resistor on the port line, it may not be added to the pull resistance.
3) The program is a corresponding transmission rate, and a NOP instruction can be added to a certain latency after the instruction of the counter line operation.
4) In order to reduce the accidental interference signal to rewrite the data in the EEPROM available external write protection pins (if any), or if there is no space in the EEPROM, you can write a sign word every time you power up or reset, It is judge whether EEPROM is accidentally rewritten.
