To understand the content of the logic level, we must first know the meaning of the following concepts:
1: Enter a high level (VIH): Ensure the minimum input high level allowed by the input of logic gates, when the input level is higher than VIH, it is considered that the input level is high.
2: Enter a low level (VIL): Ensure that the maximum input low allowed by the logic gate is low. When the input level is below the VIL, the input level is considered to be low.
3: Output High Level (VOH): Ensure the minimum value of the output level of the logic gate to high level, and the level value of the logic gate must be greater than this VOH.
4: Output Low Level (VOL): Ensure the maximum value of the output level of the logic gate to the low level, and the level value of the logical gate must be less than this Vol.
5: Valve Level (VT): There is a threshold level in the digital circuit chip, that is, the circuit just barely flipped the level of action. It is a voltage value bound to vil, ViH. For the threshold level of the CMOS circuit, it is basically one-half of the power supply voltage value, but to ensure a stable output, it must be required to enter high level> VIH , Enter a low level For a general logic level, the relationship between the above parameters is as follows: VOH> VIH> VT> VIL> VOL. 6: IOH: The logic gate outputs a load current (to pull current). 7: IOL: The logic gate outputs a load current (for ambulatory current). 8: IIH: The logic gate is input to a high electricity (for ambulance). 9: IIL: The logic gate is input to a low current (to pull current). The gate circuit output is extremely introduced directly from the integrated unit to direct the load resistance as the output, and this form of the door is called the road gate. The TTL, CMOS, and ECL doors of the open circuit are called the collector opening (OC), the drain opening (OD), the emitter opening circuit (OE), should be reviewed when using the upper pull resistor (OC, OD door) or pull-down resistor (OE door), and if the resistance resistance is appropriate. For the collector opening (OC) door, the pull-up resistance resistance value RL should satisfy the following conditions: (1): RL <(vcc-voh) / (n * oh m * iih) (2): RL> (Vcc-Vol) / (IOL M * IIL) Where N: The number of openings and openings; M: The number of inputs being driven. : Common logic level · Logic level: TTL, CMOS, LVTTL, ECL, PECL, GTL; RS232, RS422, LVDS, etc. · The logic level of TTL and CMOS can be divided into four categories: 5V Series (5V TTL and 5V CMOS), 3.3V Series, 2.5V Series and 1.8V Series. · 5V TTL and 5V CMOS logic are common logic levels. · The logic levels of 3.3V and below are called low voltage logic levels, commonly used for LVTTL levels. • The logic level of low voltage is 2.5V and 1.8V. · ECL / PECL and LVDs are differential input and output. · RS-422/485 and RS-232 are interface standards of serial ports, RS-422/485 is differential input and output, and RS-232 is single-ended input output.
