Transfer from: http://linux.chinaitlab.com/command/5602.html 2006-6-23
When developing a system, a system is generally divided into several modules, which improves the maintenanceability of the system, but because there is inevitable association between each module, other modules may be updated after a module is changed. Of course, it is no problem for the small system, and the hand-compiled connection is no problem, but if it is a large system, there are many modules, then hand-compiled methods are not applicable. To this end, in the Linux system, a Make command is specifically provided to move the target file. Compared to manual compilation and connection, the advantage of the Make command is that he only updates the modified file (in Linux, a file is created or There is a final modification time after the update, the make command is to determine whether the file is modified by this final modification), and the file that is not modified is ignored, and the make command will not miss a file that needs to be updated.
There may be dependencies between files and files or modules or modules or modules. The Make command is also maintained according to this dependency, so we need to know what is dependent; the most metaphor: If we want to play games, there must be Game disc and computer (there is a dependency between the two), and the prerequisite for game discs and computers is the necessary economic conditions, and when you have a game disc, you have to choose which game is based on your mood. ;As shown below:
play games
/
/
Game CD
/ /
/ /
Mood economy
The make command certainly does not know these dependencies, and the programmer needs to write these dependencies into a file called Makefile. The Makefile file contains some targets, usually the target is the file name, a set of commands for each target, providing this target and other objectives or file names with this target dependency, the following is a simple Makefile simple example:
# A simple makefile
PROG: PROG1.O PROG2.O
GCC PROG1.O PROG2.O -O PROG
PROG1.O: PROG1.C LIB.H
gcc -c -i. -o prog1.o prog1.c
PROG2.O: PROG2.C
gcc -c prog2.c
Three objectives were defined above the masterfile: PROG, PROG1, and PROG2, the semicolon is a list of dependencies, and the middle is separated by a semicolon;
For the first target file Prog, he has two dependencies: prog1.o and prog2.o, any dependent file update, PROG should be updated, command GCC PROG1.O PROG2.O -O PROG is Generate the command of the prog. Make checks whether the target needs to be updated, and the recursive method is updated from the underlying direction, and this goal will be updated only when all the goals depend on by a goal are updated. Take above as an example, we modified PROG2.C. When executing Make, due to the target PROG relying on PROG1.O and PROG2.O, you must first check if PROG1.O and PROG2.O are outdated, the target prog1.o relies on Prog1 .c and lib.h, because we did not modify these two files, they did not expire, then checked the target prog2.o, he rely on Prog2.c, because we have modified Prog2.c, so pROG2.C More than the target file prog2.o, the prog2.o expires, and all the goals that depend on Prog2.o are outdated; so Make will update the prog2.o and then update the prog. If a certain row is too long, it has already reached the right boundary of the text editor, and a backslash () can be used to do line characters, all rows connected to the backslash will be treated as a row; additional file names involved in makefile Allow Use wildcard (or *).
Sometimes in order to simplify the writing of the command, you can define some macros and use abbreviations in makefile. Here are a few abbreviations:
$ @ Represents the full name of this goal
$ * Represents the target name of the suffix has been deleted
$ You can use an abbreviation to make a corresponding modification of the above Makefile: # Using abbreviated Makefile PROG: PROG1.O PROG2.O GCC PROG1.O PROG2.O -O $ @ PROG1.O: PROG1.C LIB.H gcc -c -i. -o $ @ $ < PROG2.O: PROG2.C GCC-C $ *. c In a project, you may use the same file AC in several targets. If this file is modified, you need to modify all the ACs in Makefile, which is more troublesome, you can define the macro to solve this problem, macro can make Makefile more Clear: # Using abbreviations and macro Makefile Marco = prog1.o prog2.o PROG: $ (MARCO) GCC PROG1.O PROG2.O -O $ @ PROG1.O: PROG1.C LIB.H gcc -c -i. -o $ @ $ < PROG2.O: PROG2.C GCC-C $ *. c For a large project, you should write makefile very troubles, and the standard GNU software (such as Apacle) is running a configure script file to generate makefile; GNU software Automake and AutoConf are automatically generating configure tools. Developers only need to define a good macro, and Automake will generate makefine.in for AutoConf, and use AutoConf to generate Configure. To use Automake and AutoConf, you must install: GNU Automake, GNU AutoConf, GNU M4, Perl, and GNU Libtool. Suppose you have a source file Test.c, use AutoScan to generate a configure.scan file, edit this file DNL Process this File with AutoConf to Produce A Configure Script. AC_INIT (TEST.C) AC_INIT_AUTOMAKE (TEST, 1.0) DNL CHECKS for Program. AC_PROG_CC DNL CHECKS for Libraries. DNL CHECKS for Header Files. DNL Checks for Typedefs, Structures, And Compiler Characteristics. DNL Checks for Library Functions. AC_OUTPUT (MAKEFILE) The Configure.scan is then renamed CNFigure.in, then execute ACLOCAL and AutoConf, generate ACLOCAL.M4 and CONFIGURE two files: We will edit the makefile.am file, the makefile.am file contains our own defined macros and goals. Document, Automake will read this file and generate the corresponding makefile.in file based on our own defined macro: Automake_Options = Foreign Run_Prog = TEST Test_source = Test.c Next, Automake -a will be executed, so far, the Configure file has been successfully generated.
