Design mode learning 1

zhaozj2021-02-16  64

I saw the design model, and it should now be shipped.

First, you must clear the location of the design mode. It is designed after the system analysis is completed after the system analysis is completed. It is often designed to bring a problem: excessive design. Because the design mode requires an increase in classes. At the same time, we see that he is not a million drug, he is affected by the preliminary needs and system analysis.

The key is the following principles:

1. One class is best only one responsibility. I saw a person attendance design online in the first two days, trying to make the staff, including staff information and attendance information, and then a bitter: his attendance information is a document, not a database, so that the system will come up, even if he does not need attendance Information, you must also read files, because the file is large, the system is very slow. Later, some people have an idea: divide two classes: Attendance is attendance, the staff is a staff, and there is a attendance List container. This will solve problems better.

2. Multi-purpose combination, less inheritance. The so-called inheritance relationship is used to reflect the change in subclass, and the combination is a modular approach. Obviously: If inheritance, the parent class changes, the most vulnerable is a subclass. This shows that the combination ratio adopts the inheritance parent class and sub-class coupling.

3. Pack the change in a class. This is my personal opinion. The so-called change package is in the class, as mentioned earlier, every class is best only a responsibility, so we'd better encapsulate a certain type. It can be seen that the demand will affect the establishment of the mode, which can be said to affect the entire system model. Of course, this is also a so-called reduced system coupling and enhances an embodiment of system cohesiveness.

This is the basic principles of all design patterns.

转载请注明原文地址:https://www.9cbs.com/read-17528.html

New Post(0)