After a few years, I have also seen a lot of things. Sometimes I want to write something, but I always feel a lot of clues, and I have not had a pen. Recently, I have turned a "programming master rumor", and suddenly wanted to write something, right to write something in the form of reading notes. The release "rumor" on the equity is the following is the I'm of myself. I hope everyone can advise, but they don't have to be, thank you. Note: This part involves the second chapter of "Proverbs".
The CPU is the heart of the computer and is the core of the control program. Only excellent programs can only be truly prepared by truly understanding the structure and operational mechanism of the CPU. ... Drink 64 in full swing today. ============================================================================================================================================================================================================= ====================================================== CPU is indeed a computer The core, but is it necessary to understand the structure and operational mechanism of the CPU to write beautiful programs? I don't think it is. The software is hierarchical, and each layer is likely to have a beautiful software. If you want to close the layer, especially with hardware relationship, such as the operating system hardware core layer writes beautiful code, of course, it is necessary to deeply understand the structure and operational mechanism of the CPU. However, if your work is higher, then you don't actually see is no hardware CPU, but your operating system, a "virtual" machine that develops a running environment. Just like comrades in the assembly development program, it is generally not too concerned about the logic design inside the CPU. As for 64-bit machine, huh, how is it still a unknown? After all, AMD launched 64 machines, Intel did not follow it immediately, it seems that it has not yet arrived. " Open a joke, if the AMD's 64-bit machine works in 32, can I play 1.5 times the 32-bit machine performance, I will never hesitate to eliminate my Athlonxp :-) Of course, 64-bit replacement 32 is inevitable, just a time problem, brothers work hard, compose the cow's software, fully play the strength and characteristics of hardware ;-)
The RISC is when designing the CPU, only the most common instruction hardware is implemented, and other instructions simulate the method of microcode software. The CISC is an architecture of an instruction corresponding to a set of execution units. However, with the improvement of CISC operating frequency and technology, RISC has now been eclipsed. ============================================================================================================================================================================================================= ============================================== actually, some The CISC CPU is also inseparable from minimal code. For example, Intel gives it a p4 CPU out microcode patch. You can look at this link http://www.pcpop.com/news/2002/8/7779.shtml . Of course, the RISC system is now facing the powerful offensive of the CISC system CPU, and some traditional RISC server suppliers, such as IBM, Sun has introduced CISC-based servers in order to leave. However, the choice of the market is sometimes not necessarily the state of technology. After all, the biggest chip giant intel is the supporter of CISC. There is no final conclusion between RISC and CISC systems. Let's remember some shiny RISC CPU families: DEC / Compaq Alpha, MIPS, HP PA-RISC series, Sun SPARC series, IBM / MOTO POWERPC, etc., even if there is such a day CISC CPU to fade out of the rivers and lakes.
In 1989, Intel launched an 80486 chip, breaking through 100MHz, exceeding the RISC CPU. ============================================================================================================================================================================================================= ================================================================================ Documentation, its 1989 launched 486DX is 25MHz operating frequency, and the first-level cache is 16KB. If Intel is unmracted, then in this operating frequency exceeds the same RISC, I am afraid it is a problem. Although the frequency is not a unique factor in the CPU operating speed.聽聽 聽聽 聽聽 聽聽 聽聽 聽聽 聽聽 聽聽 夕 中 科 科 矣 死 矣 矣 矣 矣 矣 矣 矣 矣 子 子 子 子 子 子 子 子 子 子 子 子 子 子It is more difficult to run than them, more than Alpha is more difficult, more than Intel is hoped. We must focus on the breakthrough exceeding Intel. " 80386 provides two working modes, one as a real mode, ..., its second is the protection mode. ============================================================================================================================================================================================================= ===================================================== in accordance with Intel's manual In fact, there should be a system management mode. I didn't encounter the program in this mode, and the comrades interested, please refer to Intel's manual.
Protection between different tasks: By putting different tasks in different virtual address spaces, the isolation of different tasks (that is, the A program cannot access the B program code and data) ========== ============================================================================================================================================================================================================= ==================================== The concept of virtual space can be a bit on the game of the virtual space for the 386 protection mode. It's hard to understand, it is actually this: Suppose a program is started twice in the multi-task operating system, then your program is actually the same in the virtual space seen in the two instances, it is 0 ~ 4G, however The underlying addressing mechanism allows the same virtual address in both instances or instructions, but there are different physical addresses. We know that the software must ultimately be implemented to the hardware. If the final physical address is different, then the two programs will not interfere with each other. Of course, if you have to let the virtual address of the two programs can also correspond to the same physical address, for the operating system, a small dish, as long as the conversion table is modified, it can achieve the purpose. (See the specific addressing method below)
The "Proverbs" book gives the addressing of the 386 CPU in the protection mode of the 386 CPU to address the addressing method of the FLAT, Segmented mode. ============================================================================================================================================================================================================= ======================================================== 386CPU in entering protection Before the mode, you must initialize a lot of data structures in the main memory. According to Intel manuals own words, The contents of the protected-mode system data structures loaded into memory during softwareinitialization, depend largely on the type of memory management the protected-mode operatingsystemor executive is going to support: flat, flat with paging, segmented, Or segmented withpaging. The book is given a simple model. It may be in order to access large memory, in order to access large memory, select this approach without OS. In the current actual operating system, it will not be used in this way, it is basically FLAT, PAGING mode. Some comrades may ask, the visiting model given by "Proverbs" is not very good, easy to understand. So why don't you use this way? The reason is to support "virtual memory", and only the high-efficiency virtual memory management program can be designed after the Paging Paging mode is enabled. What is virtual memory, simply is a general application designer and a memory that some underlying operating system designer. We know that 32-bit machines can address 4G address range (actually new Intel CPU can access more than 4G physical memory through a certain way, however they can directly access the virtual memory or 4G), And the vast majority of comrades don't have so much memory, what should I do? With the Paging function, with the support of OS, you can give the programmer to provide a virtual memory, its size is 4G (of course, the current operating system does not give all 4G to ordinary programs, but retain some to OS The kernel, such as Linux seems to have left 3G virtual space to the application). This so-called "virtual memory" is implemented. To answer this question, you must start from the CPU how to get the physical address after enabling Page. Below I try to describe this process with as much as possible, try to design some of the terms of 386 protection mode. As for the official statement, please refer to Intel 386 programmer manual, this manual can be free from Intel. Give a link, so you have to search again, http://www.intel.com/design/pentium4/manuals/245470.htm.
OK, Let's Go! Here is the FLAT, PAGING mode used by some mainstream operating systems. What is FLAT, in fact, 386CPU still retains the segmentation function of the early CPU, and the FLAT mode is set to 0, and the range of this segment is set to 4G, so that there is no segmentation function. What is PAGING, which is divided into many small pieces, then map these blocks to physical memory or auxiliary memory, such as a hard disk. This explains why you can provide a large (such as 3G) memory space that can be given to normal programmers, because we can map some virtual memory to disk, and transfer them to physical memory when needed. If we disassemble some programs, you can see that from the surface, it seems that there is no difference in the way to access memory. The actual situation is that this difference is behind the scene. In fact, we are actually "virtual address" in the assembler, the formation of virtual addresses or the same as the past segment management, namely the start address plus the offset. Since all segment start addresses are 0 in FLAT mode, we specified in the assembler is the final virtual address. For example, this statement, MOVL $ 0x4321, 0x8049430, its meaning is where the integer 0x4321 is sent to the address of 0x8049430. (Sorry, since there is no development tool for the Win32 platform on my hand, I have to pick a line from the procedure that uses GDB disassembled program) in FLAT mode, 0x8049430 is the final virtual address. After getting the virtual address, the revolution has successfully successfully first, and below is to use paging management to get the final physical address. The process is taken below, first take the virtual address, that is, the high 10BITS of the 0x8049430 as an index to index "the first" table, the start address of this table is placed in the system CR3 register. Take a 32-bit integer from the "first" table, and this integer corresponds to the start address of the "second" table. Then take the middle 10 bits of the virtual address 0x8049430 to index this second table, and you can get a 32-bit value. This value is actually a physical address. With this physical address plus 12 0x8049430, 12 The value of BITS can form the physical address corresponding to the final 0x8049430. After writing the above process, I also looked back, I didn't know how to write, right? Well, we will give an example in actual life to illustrate (nonsense, since there is nothing to say, do you say :-). If you operate a big hotel, let you receive a lot of passengers from all over the country, smart, you think of a way to arrange them, every person, you have taken his ID card, (assume the ID card The format is "Provincial Name-City Name-Birth Serial No.") to find the "first" form based on his province, let him go to the office of this province. After the passenger went to the office of the province, there was a reception staff to take his ID card according to the next city information, "Second" form, arranged him to the floor of the city's passenger. After the passenger reaches the corresponding floor, find its own room according to your birth order. Maybe you have to ask, do you have to arrange an action in accordance with the province, do you have to arrange the corresponding city's corresponding office? The reason is to save a few offices, some provinces have no plans, so smart, you have no arrangements for this province's underlying cities, come to a person, you can know this person according to his province, you should know that this person should not know Reception, otherwise, if you have a waste every city, it is a waste, especially if your guests are only concentrated in several specific provinces.
The situation in which our procedure is "only in several specific provinces", so it takes two-level index to save the size of the table required to maintain the paging mechanism. If so, we assume that a small piece of unit is 4K bytes, then map 4G space we need 4m 4K bytes to save the form you need to page. (This value is calculated, "The first" table is 4K size, with 1024 entries, each entry corresponds to a "second" table, which has 1024 second tables, and each The second table size is also 4K, so I need 4M space to put "second" table) Oh, I have a half day, I don't know if it is clear. Comrade this part of interest can be further refer to the Intel manual and Linux boot code. In addition, a very important concept of protection mode is "Protection", the paragraph inside the system, the page has a lot of attributes and permissions, and the low-rights code does not adjust the instructions of higher privileges. You think about it, if this is not the case, the user program will change the two forms, isn't it an address that can be accessed, huh, huh. Some virus codes have digns to make the virion to run under the highest privilege level of the CPU, and the CIH virus is a good proof. Oh, yes, this link http://jiuml.nease.net/document/jiumplaywin2k/mmpaging1.htm gives the paging mechanism than what I speak, I can go see. If you have comrade to write your own small test program, it is recommended to download Bochs on the SourceForge, an X86 simulator, which is at least exempt from your Reboot Computer's troubles. For the interrupt processing of 386, "rumor" gives a description of a page. ============================================================================================================================================================================================================= ============================================================================================================================================================================================================= === It is a few chapters in the intel manual. I have almost never touched this piece, huh, it is time to do it, I am directly closed, huh, huh. Comrades can also refer to the Intel manual and Linux interrupt processing section. I hope that there is comrades to post the post to describe the processing method of the 386 interrupt.
About the example program attached to "Proverbs" ========================================= ======================================================================================================================================================================================== There is no pure DOS environment. Just have a few questions, I don't know the answer, I hope to understand the comrades: 1) There is no 4G memory, then there is no corresponding physical device, I don't know if I don't know if I have access to these addresses. Leading system abnormalities. 2) In accordance with Intel's manual, enter the protection mode requires a long jump, and the sample program is a partial short jump. I don't know if it is really like "rumors". In addition, English comments in the "Proverbs" program do not understand, hopes to understand comrades. 3) Since there is only 64K in the real mode, then how do we access all memory through FS in real mode? Oh, have the opportunity to try it with Bochs. Today, I saw an article on the Internet. Let's take a look, then in charge of "rumors", what do you think? http://www.lisoleg.net/lisoleg/memory/
