These days have been exposed to SYSTEMC, some feelings:
1. SYSTEMC is a set of C Class Library that extends C into a hardware description language (HDL). I feel that learning SYSTEMC should be at least two things: C , one hardware description language. I am familiar with C , and I am familiar with Verilog, so I learned SYSTEMC to raise an anticipation.
2. SYSTEMC uses many features of C : multiple inheritance, virtual inheritance, template, RTTI (At Least for Dynamic_cast), exception handling, operator overload. It seems that there is no use of STL.
3. Systemc is a set of Application Framework, personal feelings, even with MFC:
Some Somewhat weird macros: SC_METHOD, SC_THREAD, SC_CTOR, etc. A global manager sc_simcontext (similar to the cwinapp in the MFC), can get the address of the global object with SC_GET_CURR_SIMCONTEXT () (similar to the AFXGetApp ()) main () hiding In SystemC, you have to do a SC_MAIN () function as an entry of the program, and SystemC will call your SC_MAIN () using table driver technology, just like the Message transfer in the MFC. SYSTEMC is registered in the global table with those macros of the SYSTEMC to register the Class (Systemc called Module). The application will then call your code based on an event that occurs.
4. From implementation, Systemc has its own Garbage Collector, its Memory Pool, its own container (replacing STL).
Personal experience: SYSTEMC uses steps under WinXP VS.NET 2003
1. SYSTEMC is released in the source code, first compile a library file using VC7.1: systemc.lib
2. The systemc program we wrote is actually a C program, write a systemc program (or design), compile the Object file with the C compiler, and then get the executable file with the Systemc.lib link.
3. Execute this EXE file to simulate. From the output (file or stdout), the simulation results are known.
Attachment: a simplest SYSTEMC MODULE
#include "systemc.h"
// Halfer
Struct Half_adder: SC_Module {SC_IN
A, B;
SC_OUT
SUM, Carry;
Void prc_half_adder () {SUM = a ^ b; carry = a & b;
SC_ctor (HALF_ADDER) {SC_METHOD (PRC_HALF_ADDER); SENSITIVE << a << b; // a, b is in sensitive list}}
Equivalent Verilog Design:
Module Half_Adder (A, B, Sum, Carry);
INPUT A, B; OUTPUT SUM, Carry; Reg Sum, Carry; ALWAYS @ (a or b) // A, B in sensitive list Begin SUM = a ^ b; carry = a & b; end / * above five lines Replace with: Assign Sum = a ^ b; Assign Carry = a & b; * / endmodule
I use the reference book: "SystemC Basic Tutorial" J.BHASKER, Sun Haiping and other translations, Tsinghua University Press.
Ping, the translation of this book is not bad, basically can read it.
