From 9CBS - Document Center - Other HaoEl [Original] Sixth, multi-line variables There is also a way to set variable values to use the define keyword. The value of setting the variable using the define keyword can have a wrap, which facilitates the definition of a series of commands (before we told the "command package" technology to use this keyword). The define indicator is followed by the name of the variable, and restarts the value of the defined variable, the definition is the end of the Endef keyword. Its work mode is the same as the "=" operator. The value of the variable can contain functions, commands, text, or other variables. Because the command needs to begin with the [Tab] key, if you don't start with the [Tab] button with the defined command variable, Make will not think it is a command. The following example shows the usage of define: Define TW-LINES Echo foo echo $ (bar) Endef seven, environment variables Make runtime system environment variables can be loaded into the Makefile file when Make starts running, but if Makefile This variable has been defined, or this variable is brought by the Make command line, then the value of the system's environment variable will be overwritten. (If Make specifies the "-e" parameter, the system environment variable will override the variable defined in Makefile), so we can use the "cflags" environment variable in the environment variable, then we can use in all makefiles. This variable is. This has a relatively good benefit to our compilation parameters. If you define cflags in makefile, this variable in makefile will use the value of the system environment variable, a common and personalized unity, which is very similar to the "global variable" and "local variable" if it is not defined. When Make nested (see chapter "Nested Call chapter), the variable defined in the upper Makefile will be passed to the lower Makefile in the way system environment variables. Of course, by default, the variables set by the command line will be passed. And define the variables in the file, if you want to pass down MakeFile, you need to use the exprot keyword to declare. (See the previous chapter) Of course, I don't recommend that many variables are defined in the system environment, so that when we don't have to make Makefile, it has the same set of system variables, which may bring more trouble. 8. The variables we are talking to the target variable are all "global variables", and we can access these variables throughout the file. Of course, except "automated variables", such as "$ <", such as "$ <" belongs to the "rule variable", and the value of this variable depends on the rules and definitions of dependent targets. Of course, I can also set local variables for a target. This variable is called "target-specific variable", which can be with "global variable", because its role range is only in this rule and the joint rules Therefore, its value is only valid within the scope of action. The value of global variables other than the rule chain will not affect the rule chain. Its syntax is:
:
: Overide
It can be various assignment expressions, such as "=", ": =", " =" or "? =". The second syntax is to target the variables brought by the Make command line or the system environment variable.
This feature is very useful, when we set a variable, this variable will act to all rules caused by this goal. Such as: prog: cflags = -g prog: prog.o foo.o bar.o $ (cflags) prog.o foo. bar.o prog.o: prog.c $ (cc) $ (cflags ) Prog.c foo.o: foo.c $ (cc) $ (cflags) foo.c bar.o: bar.c $ (cc) $ (cflags) bar.c In this example, no matter the global $ What is the value of cflags, in the PROG target, and all the rules it triggered (Prog.o Foo. bar.o rules), the value of $ (cflags) is "-g" nine, mode variables In the GNU's Make, the pattern variable is supported. In the above target variable, we know that the variable can be defined on a target. The advantage of mode variables is that we can give a "mode" to define variables on all targets that meet this mode. We know that Make's "mode" is generally at least one "%", so we can define target variables in [.o] at the end of [.o] in the following way:% .o: cflags = -o, mode The syntax and "target variable" of the variable:
: OVERRIDE
OVERRIDE is also a variable that is incorporated on the system environment, or the variable specified by the Make command line. Use condition judgment ------ Use condition judge, allowing Make to select different execution branches depending on the different conditions of runtime. The conditional expression can be a value of a comparison variable, or a value of comparison variables and constants. First, the example below, determines if the $ (CC) variable "GCC", if yes, use the GNU function to compile the target. Libs_for_gcc = -lgnu Normal_Libs = Foo: $ (Objects) IFEQ ($ (CC), GCC) $ (CC) -o Foo $ (Objects) $ (libs_for_gcc) ELSE $ (CC) -o Foo $ (Objects) $ ( NORMAL_LIBS) ENDIF visa We can see three keywords from the above example: IFEQ, Else, and Endif. IFEQ means the beginning of the conditional statement, and specifies a conditional expression, the expression contains two parameters, separated by commas, and the expression is enclosed in parentheses. Else indicates the condition of the conditional expression. Endif indicates the end of a conditional statement, and any conditional expression should end with ENDIF. When our variable $ (cc) value is "GCC", the rules of the target foo are: foo: $ (Objects) $ (cc) -o foo $ (objects) $ (libs_for_gcc) while our variable $ (cc) The value is not "GCC" (such as "cc"), the rules of the target foo are: foo: $ (ibjects) $ (cc) -o foo $ (objects) $ (Normal_Libs) Of course, we can also put the above Examples are more concise: libs_for_gcc = -lnu Normal_Libs = IFNU NORMAL_LIBS = IFEQ ($ (cc), gcc) Libs = $ (libs_for_gcc) Else Libs = $ (Normal_Libs) Endif Foo: $ (Objects) $ (cc) -o foo $ (Objects) $ (libs) Second, the syntax of the syntax condition expression is: ENDIF
as well as:
Else
ENDIF
among them
Indicates the keyword, such as "IFEQ". This keyword has four.
The first is "IFEQ" IFEQ before we have seen.
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IFEQ '
'' '
'
IFEQ "
""
"
IFEQ "
"'
'
IFEQ '
""
"
The value of comparison parameters "arg1" and "arg2" are the same. Of course, we can also use the Make function in the parameter. Such as: IFEQ ($ (Strip $ (Foo)),)
ENDIF
The "strip" function is used in this example. If the return value of this function is empty, then
Effective.
The second condition key is "ifneq". Grammar is: IFNEQ (
,
)
IFNEQ '
'' '
'
IFNEQ "
""
"
IFNEQ "
"'
'
IFNEQ ''
"
Its comparison parameter "arg1" and "arg2" are the same, if different, it is true. Similar to "IFEQ". The third condition key is "IFDEF". Grammar is: ifdef
If the variable
The value is not empty, then the expression is true. Otherwise, the expression is false. of course,
It can also be a return value of a function. Note that ifdef only tests if a variable has a value, it does not extends the variable to the current location. Or come to see two examples:
Example 1: bar = foo = $ (bar) ifdef foo frobozz = yes else frobozz = no endif example: foo = ifdef foo frobozz = yes else frobozz = no Endif's first example, "$ (frobozz) value is "Yes", the second is "no". The fourth condition key is "ifndef". Its syntax is: IFNDEF
I don't have much to say this, and "ifdef" is the opposite. in
On this line, excess space is allowed, but you can't start with the [Tab] key (otherwise it is considered a command). The comment "#" is also safe. "Else" and "Endif" are the same, as long as it is not to start with the [Tab] button.
In particular, Make is the value of the conditional expression when reading Makefile, and selects the statement according to the value of the conditional expression, so don't put the automated variables (such as "$ @", etc.) In the conditional expression, since the automation variable is only running. Moreover, in order to avoid confusion, MAKE does not allow the entire condition statement into two parts in different files. <- Previous Next -> (All rights reserved, please indicate the author and source)
