From 9CBS - Document Center - Other Haoel [Original] Six, the goal in the rules of multi-objective makefile can be more than one, it supports multi-objective, it is possible that our multiple goals depend on one file, and its generated commands are generally similar . So we can merge them. Of course, the execution command of the generation rules of multiple targets is the same, which may have to bring trouble, but in our use of an automated variable "$ @" (about automated variables, it will be described later), this Variables show a collection of all goals in the current rules, which may be abstract, or look at an example. BIGOUTPUT LITTLEOUT: TEXT.G Generate Text.g - $ (Subst Output, $ @)> $ @ 上 规 规 等 等 价 于于: g -little> LittleOutput, "$" in-$ (subst output, $ @) means executing a MakeFile function, the function is called subst, which is the parameter. About the function will be described later. This function here is the meaning of the string, "$ @" indicates the collection of the target, just like an array, "$ @" takes out the goal, and it is committed to the command. Seven, static mode static mode can be more easily defined for multi-objective rules, allowing us to make our rules more flexible and flexible. Let's first look at the syntax first:
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Targets defines a range of target files that can have wildcards. Is a collection of goals. Target-Parrtern is a model of Targets, that is, the target set mode. Prereq-Parrterns is the dependency mode of the target, which is defined for the mode of Target-Parrtern. This three things may still be clear, or an example to explain it. If our
Define into "% .o", meaning our
The collection is ended with ".o", and if we
Define into "% .c", meaning
The target set formed is defined in the secondary definition.
"%" In the mode (that is, the end of [.o] is ended), and adds the new collection of [.c].
So, our "target mode" or "dependency mode" should have "%" characters, if you have "%" in your file name, you can use a backslash "/" to indicate, to indicate Real "%" characters. See an example: Objects = foo.o bar.o all: $ (objects):% .o:% .C $ (cc) -c $ (cflags) $ @ 上 上Indicates that our goals are got from $ Object, "%. O" indicates all the goals ending with ".o", that is, "foo.o bar.o", that is, the variable $ Object Collection mode, and Dependent mode "% .C" is "% .o" "%", which is "foo bar", and add ".c" suffix, so our dependence is "foo.c" Bar.c. The "$ <" and "$ @" are automated variables in the command, "$ <" indicates that all dependence target sets (that is, "foo.c bar.c"), "$ @" indicates the target set (also It is "foo.o bar.o"). As a result, the following rules are equivalent to the following rules: foo.o: foo.c $ (cc) -c $ (cflags) foo. c c foo.o bar.o: bar.c $ (cc) -c $ (cflags) bar.c -o bar.o, if we "% .o" has hundreds, then we can write a bunch of "Static Mode Rules" with this very simple "Static Mode Rule" Rules are really efficient. The Usage of Static Mode Rules is flexible, if you are used, it will be a very powerful feature. Look at an example: files = foo.elc bar.o lose.o $ (Filter% .o, $ (files)):% .o:% .C $ (cc) -c $ (cflags) $ <-O $ @ $ (File% .elc, $ (files)):% .elc:% .el emacs -f batch-byte-compile $ <$ (file% .o, $ (files) indicating the Filter function called Makefile Filter the "$ FILTER" set, as long as the mode is "% .o". Its content, I don't have to say more. This example shows greater flexibility in makefile. 8. Automatic generation dependency in Makefile, our dependencies may need to include a series of headers, such as if there is a "#include" defs.h "in our main.c, then our dependency It should be: main.o: main.c defs.h However, if it is a relatively large engineering, you must know which C files contain which headers, and you need to be careful when you join or delete the header file. Modify Makefile, this is a very maintenance of work. In order to avoid this heavy and easy error, we can use a function of compilation of C / C . Most C / C compilers support a "-m" option, that is, automatically find the header files contained in the source file and generate a dependency.
For example, if we perform the following command: cc -m main.c Output is: main.o: main.c defs.h is then automatically generated by the compiler, so that you don't have to manually write a number The dependencies of the document are automatically generated by the compiler. It is necessary to remind a sentence that if you use the GNU's C / C compiler, you have to use the "-mm" parameter, otherwise, "-m" parameters will also include some standard libraries' header files. The output of gcc -m main.c is: main.o: main.c defs.h /usr/include/stdio.h /usr/include/features.h //usr/include/sys/cdefs.h / usr / Include / gnu / stubs.h //usr/lib/gcc-lib/i486-suse-linux/2.95.3/include/stddef.h //usr/include/bits/types.h / usr / include / bits / PthreadTypes.h / /usr/include/bits/sched.h /usr/include/libio.h / /usr/include/_g_config.h /usr/include/wchar.h / /usr/include/bits/wchar.h /usr/include/gconv.h //usr/lib/gcc-lib/i486-suse-linux/2.95.3/include/stdarg.h //usr/include/bits/stdio_lim.h gcc -mm main.c The output is: main.o: main.c defs.h So, how the compiler is associated with our makefile. Because in this way, our makefile should also regenerate according to these source files, let Makefile dependent on the source file? This feature is not realistic, but we can have other means to go back to this function. The GNU organization recommends putting the compiler to automatically generated dependencies of each source file in a file, generate a "name.d" Makefile file for each "name.c" file, [D] file Store the dependency of the [.c] file in place. Thus, we can write the [.c] file and [.d] file dependency, and let the make automatically update or self-contained [.d] files, and contain it in our master makefile, so we will It can automatically generate the dependence of each file.
