How to Write a Makefile17: 32: 18
Introduction
Make Is One of the Original Unix Tools for Software Engineering. By S.I. Feldman of AT & T Bell Labs Circa 1975. But There Are Public Domain Versions for Other Systems (EG. VAX / VMS).
Related Tools Are The Language Compilers (CC, F77, LEX, YACC, ETC.) and shell Programming Tools (Eg. Awk, sed, cp, rm, etc.). You need to know how to use.
Important Adjuncts Are Lint (Source Coding for Obvious Errors) CTags (Locate Functions, etc. In Source Code) and mkdepend. These is Nice, And Good Programmers Use.
Important, And Related Tools, Are The Software Revision Systems Sccs (Source Cogn Control System) And RCS (Revision Control System - The Recommended Choice)
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Makefile Namingmake is going to look for a file called Makefile, if not found then a file called makefile. Use the first (so the name stands out in listings). You can get away without any Makefile (but should not)! Make has Default Rules It Knows About.
Makefile ComponentsComments "area, syxt beginning with the point, sign. A comment can start anywhere on a line and contact until the end of the line. For example:
# $ ID: SLIDES, V 1.2 1992/02/14 21:00:58 Reggers EXP $
Macro Definition and Substitution Mechanism. Macros Are Defined IN A Makefile As = Pairs. For Example:
Macros = -mepsroff = groff -tpsditroff = groff -tdvicflags = -o -systype BSD43
. There are lots of default macros - you should honor the existing naming conventions To find out what rules / macros make is using type:% make -pNOTE: That your environment variables are exported into the make as macros They will override the defaults. You can set Macros on the make command line:
% make "cflags = -o" "ldflags = -s" printenv cc -o protetenv.c -s -o protetenv
Targetsyou make a particular target (eg. Make all), in none specified the first target found:
Paper.dvi: $ (SRCS) $ (Macros) $ (srcs)> Paper.dvi
NOTE: The the line beginning with $ (DITROFF) begins with TAB not spaces.The target is made if any of the dependent files have changed The dependent files in this case are represented by the $ (SRCS) statement..
Continuation of linesuse a back slash (/). This is important for long macros and / or rules.
Conventional Macrosthere Are Lots of Default Macros (Type "make -p" to print out the defaults). MOST ARE PRETTY OBVIOUS from The Rules in which
AR = arGFLAGS = GET = getASFLAGS = MAS = masAS = asFC = f77CFLAGS = CC = ccLDFLAGS = LD = ldLFLAGS = LEX = lexYFLAGS = YACC = yaccLOADLIBS = MAKE = makeMAKEARGS = 'SHELL = / bin / sh'SHELL = / bin / shMAKEFLAGS = B
Spectial Macrosbefore Issuing Any Command IN A Target Rule Set There Certain Special Macros Predefined.
$ @ is The name of the file to be my name. $? is The names of the change dependents. so, for example, we could use a rule
Printenv: Printenv.c $ (CFLAGS) $? $ (ldflags) -o $ @
Alternatively: Printenv: Printenv.c $ (cc) $ (cflags) $ @. c $ (ldflags) -o $ @
There is: $ Makefile Target Rulesthe General Syntax of A Makefile Target Rule IS Target [target ...]: [Dependent ....] [Command ...] Items in brackets are optional, ellipsis means one or more. Note the tab to preface each command is required. The semantics is pretty simple. When you say "make target" make finds the target rule that applies and, if any of the dependents are NEWER THAN THE TARGET, MAKE EXECUTES The COM- MANDS One At A Time (After Macro Substitution). IF Any Dependents Have To Be Made, That Happens First (SO You Have A Recursion). A Make Will Terminate IF ANY Command Returns A Failure Sta- Tus. That's why you see rules like: Clean: -rm * .o * ~ Core Paper Make ignores the returned status on command lines that begin with a dash. Eg. Who cares if there is no core file? Make will echo the commands, after macro substition to show you what's happening as it happens. Sometimes you might want to turn that OFF. for example: Install: @echo you must be root to install Example Target Rulesfor Example, To Manage Sources Stored Withnin RCS (Sometimes You'll Need To "Check Out" a Source File): SRCS = X.C Y.c Z.c $ (Srcs): Co $ @ To Manage Sources Stored With SCCS (Sometimes You'll Need to "get" a source file): $ (srcs): sccs get $ @ Alternativley, To Manage Sources Stored within Sccs or RCS Let's Generalize with a Macro That We can set as required. Srcs = x.c y.c z.c # get = sccs getget = CO $ (SRCS): $ (GET) $ @ For Example, To Construct A Library of Object Files Lib.a: x.o y.o z.o Ar rvu lib.a x.o y.o z.o ranlib lib.Aalternative, to be a bit more fan you could use: obj = x.o y.o z.oar = ar LIB.A: $ (OBJ) $ (ar) rvu $ @ $ (bj) ranlib $ @ Since ar is a default macro already assigned to "ar" you can get away without defining it (but shouldn't). If you get used to using macros You'll Be Able To Make A Few Rules That You Can CAN Use over and over Again.for EXAMPLE, TO Construct a Library in Some Other Directory INC = .. / mischathers = .. / Misc / lib.a $ (Others): CD $ (inc); make lib.a BEWARE: HEOUWING WILL NOT WORK (But You'd Think IT Should) Inc = .. / Miscothers = .. / Misc / Lib.A $ (Others): CD $ (inc) make lib.a Each Command in The Target Rule Is Executed in a Separate Shell. This Makes for Some Interesting Constructs and long Contination Lines. To Generate A Tags File SRCS = x.c y.c z.cctags = ctags -x> tags Tags: $ (srcs) $ {ctags} $ (srcs) On Large Projects A Tags File, That Lists All Functions and Their Invocations Is A Handy Tool. To Generate A LISTINGLYELY BUGS IN Your Problems Lint: LINT $ (CFLAGS) $ (SRCS) Lint Is a really good tool for Finding Those Obvious Bugs That Slip Into Program, Eg. Type Classes, Bad Argu- Ment List, ETC. Some Basic Make Rule People have come to expect certain targets in Makefiles. You should always browse first, but it's reasonable to expect that the targets all (or just make), install, and clean will be found. make all - should compile everything so that you can do local testing before installing things make install -.. should install things in the right places But watch out that things are installed in the right place for your system make clean -. should Clean Things Up. Get Rid of The Executables, Any Temporary Files, Object Files, etc. You May Encounter Other Common Targets, Some Have Been Already Mentioned (tags and lint) .an Example Makefile for Printenv # Make the printenv command # OWNER = binGROUP = binCTAGS = ctags -x> tagsCFLAGS = -OLDFLAGS = -sCC = ccGET = coSRCS = printenv.cOBJS = printenv.oSHAR = sharMANDIR = / usr / man / manl / printenv.lBINDIR = / USR / local / Bindepend = MAKEDEPEND $ (CFLAGS) All: Printenv # To get Things Out of The Revision Control System $ (SRCS): $ (GET) $ @ # to make an object from Source $ (CC) $ (cflags) -c $ *. C # To make an executable Printenv: $ (OBJS) $ (CC) $ (LDFLAGS) -O $ @ $ (OBJS) # To Install Things in The Right PlaceInstall: Printenv Printenv.mn $ ($ 19) -M 755 Printenv $ (BINDIR) $ (Install) -c-o $ (Owner ) -g $ (group) -m 644 Printenv.man $ (MANDIR) # Where are Functions / Procedures? Tags: $ (srcs) $ (CTAGS) $ (srcs) # What have I DONE WRONG? LINT: $ (SRCS) LINT $ (CFLAGS) $ (SRCS) # What Are the Source DependencialEndencial - $ (SRCS) $ (SRCS) # To make a shar distibutionshar: Clean $ (Shar) Readme Makefile Printenv.man $ (srcs)> Shar # c o u *.. * .bak core tags shark # Do not delete this line - make dependends on it.printenv.o: /usr/include/stdio.h Makefile Implicit Rulesconsider The Rule We Used for Printenv Printenv: Printenv.c $ (CFLAGS) Printenv.c $ (ldflags) -o Printenvwe Generalized A bit to get Printenv: Printenv.c $ (cc) $ (cflags) $ @. C $ (ldflags) - o $ @ THE COMMAND IS One That OUGHT TOWORK IN ALL X out of the source code xc this can be stated as an on omplicit rule: .c: $ (cc) $ (cflags) $ @. C $ (ldflags ) -o $ @ This Implicit rule says how to make x out of xc -.. Run cc on xc and call the output x The rule is implicit because no particular target is mentioned It can be used in all cases Another common implicit rule is for the construction. OF .O (Object) FILES OUT OF .C (Source Files). .O.c: $ (cc) $ (cflags) -c $ Alternatively .O.c: $ (cc) $ (cflags) -c $ *. Make Dependenciesit's Pretty Common To Have Source Code That Uses Include Files. For example: % Cat Program.c #include #include "Defs.h" #include "glob.h" etc .... main (argc, argv) ETC ... The implicit rule only covers part of the source code depen- dency (it only knows that program.o depends on program.c) The usual method for handling this is to list the dependen- cies separately;. Etc ... $ (CC ) $ (Cflags) -c $ *. C etc ... Program.o: program.c defs.h glob.h Usually an implicit rule and a separate list of dependencies is all you need. And it ought to be easy enough to figure out what the dependencies are. However, there are a number of nice tools around that will automatically generate dependency lists for you. For Example (TRIVIAL): Depend = makedepend $ (cflags) etc ... # What are the source dependencies Depend: $ (SRCS) $ (Depend) $ (srcs) ETC .... # do not delete this line - .... Printenv.o: /usr/include/stdio.hthese Tools (mkdepend, mkmkf, etc.) Are Very Common these Days and aren't Too Difficult To Use or understand. They're Just Shell Scripts That Run CPP (OR CC - M, or etc.) to find out what all the include dependencies are. The Dependency List ONTO The End of The Makefile. Based ON Make and Makefiles by Reg Quinton Computing and Communications ServicesThe University of Western Ontariolondon, Ontario N6A 5b7canada -------------------------------------------------- .
