Peripheral Interconnection (PCI) is a bus standard that connects to the external equipment in the system to be connected to control, including electrical characteristics and behavior of system components. This chapter will discuss the initialization process of the Linux core to the PCI bus and the device in the system. Figure 6.1 A PCI-based system schematic diagram 6.1 is a system schematic of a PCI-based system. The PCI bus and the PCI-PCI bridge are in the connection system to the upper key role. In this system, the CPU and video devices are connected to the PCI Bus 0, which is the main PCI bus in the system. The special PCI device of the PCI-PCI bridge connects the main bus PCI bus 0 to the lower level bus PCI BUS 1. In the PCI standard terminology, PCI BUS 1 is DOWNSTREAM of the PCI-PCI bridge and PCI bus 0 is the UP-stream of this bridge. SCSI and Ethernet devices are connected to this system through the secondary PCI bus. In the physical implementation, the bridge and the secondary PCI bus are integrated into a PCI card. The PCI-ISA bridge is used to support ancient ISA devices, and there is a high-level I / O control chip to control the keyboard, mouse, and floppy disk devices. 6.1 PCI address space CPU and PCI devices need to access memory space shared between them. This memory area is driven by the device to control the PCI device and transmit information between the CPU and the PCI device. The most typical shared memory includes the control and status register of the device. These registers are used to control the device and read their information. For example, the PCI SCSI device driver can find the SCSI device that is ready to write a piece of data into the SCSI disk. At the same time, it is also possible to start the device by writing information on the control register after power-on. The CPU system memory can be used as this shared memory, but if this approach, each PCI device accesses this memory block, the CPU will be forced to stop working to wait for the PCI device to do this. This way to limit shared memory to only one system device access. This policy will greatly reduce system performance. However, if you allow system peripherals to access the main memory is not a good way. Its danger is that a malicious behavior will enable the entire system in an unstable state. It has its own memory space. The CPU can freely access this space, but the device will be under the strict control of the DMA (Direct Memory Access) channel. ISA devices need to access two address spaces: ISA I / O (input and output) and ISA memory. The PCI device needs to access three address spaces: PCI I / O, PCI memory and PCI configuration space. The CPU can access all of these address spaces. PCI I / O and PCI Memory are used by device drivers and PCI configuration spaces are used by PCI initialization code in the Linux core. The Alpha AXP processor cannot access these address spaces as free as accessing the system address space, which can only access these address spaces through the auxiliary chipset, such as the PCI configuration space. The Alpha AXP processor uses a sparse address mapping policy to "steal" from the huge virtual memory of the system and map it to the PCI address space. 6.2 PCI Configuration First Map 6.2 PCI Configuration Each PCI device in the header system, including the PCI-PCI bridge, has a configuration data structure, which is usually located in the PCI configuration address space. The PCI configuration head allows the system to identify and control devices. Configure the position of the head in the PCI configuration space depends on the topology of the PCI device in the system. For example, insert a PCI video card into a different PCI slot, which changes the header position. However, there is no impact on the system, and the system will find each PCI device and the bridge and use the information in their configuration header to configure its register. A typical approach is to determine the offset of its PCI configuration head in the configuration space with the PCI slot relative to the motherboard. For example, the PCI configuration header of the first PCI slot in the motherboard is located at the configuration space offset 0, and the second is located at the offset 256 (all PCI configuration head lengths are equal, 256 bytes), and other grooves can be Such push. The system will also provide a hardware-related mechanism so that the PCI setting code can correctly identify the PCI configuration header of all existing devices on the PCI bus.
By the PCI configuration header to determine which devices exist and which devices do not exist (this domain called vendor flag field: vendor identification field). The read operation of this domain in the empty PCI slot will result in an error message value of 0xFffffFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF Figure 6.2 shows the structure of the 256-byte PCI configuration header, which contains the following domain: Vendor Identification is used to uniquely identify the value of the PCI device manufacturer. Digital's PCI vendor is identified as 0x1011 and Intel is 0x8086. Device Identification is used to uniquely identify the value of the device. Digital 21141 The device identifier of the fast Etheri equipment is 0x0009. Status This domain provides status information for this device in the PCI standard definition. Command (Command) can control this device by writing to this domain, such as allowing the device to access the PCI I / O memory. Class Code Code This domain identifies the type of this device. For each type of video, SCSI and other devices have standard classification code. If the SCSI device classification code is 0x0100. Base Address Registers These registers are used to determine and assign the type, quantity and location of the PCI I / O and PCI memory spaces that this device can use. The four physical pins on the Interrupt pin PCI card can bring the interrupt signal from the card to the PCI bus. The four pins standards are labeled as A, B, C, and D. The interrupt pin domain describes the pin number used by this PCI device. Usually specific devices are hard-connected ways. This is also the system startup, the device always uses the same interrupt pin. Interrupt processing subsystems use it to manage interrupts from the device. Interrupt Line This device configuration header is used to transfer interrupt processing between PCI initialization code, device driver, and Linux interrupt processing subsystem. Although this value recorded in this domain is meaningless to device drivers. However, it can route the interrupt process from the PCI card to the corresponding device driver interrupt processing code in the Linux operating system. The Linux interrupt processing process will be described in detail in the Interrupt chapter. 6.3 PCI I / O and PCI Memory Addresses These two address spaces are used to implement communication between device drivers in the PCI device and Linux core. For example, the internal register of the DEC 21141 quickly Ethernet device is mapped to the PIC I / O space, the corresponding Linux device driver can be controlled by reading writing of these registers. PCI video cards typically use a large number of PCI memory space to store video information. The system will never access them before the PCI system is established and opened these address spaces by using the command domain in the PCI configuration header. It is worth noting that only the PCI configuration code reads and writes the PCI configuration space, the Linux device driver reads only write the PCI I / O and PCI memory addresses. 6.4 PCI-ISA Bridge This bridge supports an old ISA device by converting access to PCI I / O and PCI memory spaces to access to ISA I / O and ISA memory. Many motherboards in the market include several ISA bus slots and PCI slots. But in the future, the backward compatibility support for ISA devices will gradually weaken, and there will be only a PCI slot on the final motherboard. Early Intel 8080 PC fixed the ISA address space of the ISA device. Even in the ALPHA AXP system worth 5,000, its ISA floppy controller address is also the same as the earliest IBM PC. The PCI standard reserves the low-end portion of PCI I / O and PCI memory to ISA peripherals in the system, and also uses the PCI-ISA bridge to access the transmission of ISA memory access from the PCI-ISA bridge. 6.5 PCI-PCI Bridge PCI-PCI Bridges is a special PCI device that connects all PCI buss in the system. There is only one PCI bus in a simple system, and the number of PCI devices connected is limited due to the limitations of electrical characteristics. The system can use more PCI devices after introducing a PCI-PCI bridge. This is very important for high performance servers. Linux provides comprehensive support for the PCI-PCI bridge.
