Any program is running on your computer to run a certain operating environment, and the operating system is of course no exception. The operating environment of the operating system mainly includes a hardware environment of a computer system and a software environment formed by other system software. In the process of learning the operating system, you must understand the specific details of the operating system and hardware environment interaction, namely the basic principles of the central processor, storage system, interrupt mechanism, I / O technology, and clock. The content and concepts of this chapter are more, but as long as they understand the basic principles of central processors, storage systems, interrupt mechanisms, I / O technology, and clocks, and can further analyze and understand the joint relationship between them. I believe there should be a deeper grasp. The following will be described separately:
Ø Hierarchy of computer system
Let us consider a computer system as a hierarchical structure, all subsystems in the computer system can include two hierarchies of the hardware (sub) system and software (sub) system.
Hardware subsystem
Hardware subsystem
Central Processing Unit (CPU)
Main memory
Outer memory
Input output device
(Keyboard / Mouse / Display / Printer ...)
Ø CPU status (homogenic and gaze) and state conversion
First understand the basic working principle of the CPU, then we will focus on the CPU status (homogeny and genius) and status conversion.
1. Processor (CPU) is generally composed of arithmeters, controllers, a series of registers and cache composition computing: implementing arithmetic and logical operations in the instruction, is the core of computer calculation. Controller: Responsible for the process of controlling program, including taking instructions, maintaining CPU status, CPU and memory interaction. Register: Provides a certain storage capacity for the CPU itself, which is much more faster than the main memory, and is used to temporarily store data, address, and instruction information during the CPU execution instruction. There are usually two types of registers: the user can use register and control registers. User registers are available to all programs, including data registers, address registers, and conditional code registers. Control registers include: Program Counter (PC: Program Counter), which records the address of the instruction to take out; the instruction register (IR: IR: Instruction Register), the recently removed instruction; Program Status Word (PSW: Program Status Word), It records the running mode information of the processor.
2. The basic process processor executed by the instruction reads an instruction from the memory, and after the instruction is completed, the program counter value is automatically turned to the address of the next instruction according to the instruction category, and then the instruction taken is placed in the instruction. In the register, the processor then explains and executes this instruction. One such single instruction processing is referred to as an instruction cycle, and the execution of the program is to constitute an instruction cycle of the instruction and execution instructions.
3. CPU Status Now multi-tasking operating system usually does not allow all instructions in a computer system, and the operating system can perform certain privileges, and the user can only use non-privileged instructions. If the user is not used during the execution of the application The privilege command must switch the CPU status to the tube state (the status of the operating system management program: Have a higher privilege level), in general, the user is in a location (lower privilege level). The only way to convert the unique way from gentle to homes is to pass the interrupt (which will be described later), interrupt the response to the interrupt vector, the working status bit flag in the new interrupt vector in the CPU program status word (PSW) register Set to a hin, and when the system is started, the initial state of the CPU is a hin state, load an operating system, and allows the user program to execute when the operating system exits. To give an example, Intel's X86 series processor (including 80386, 80486, Pentium, Pentium Pro, Pentiumii, Pentiumiii, and the current Pentium processor), providing 4 privilege levels (privilege: R0, R1, R2 and R3). The larger numbers represent lower privileges. R0 runs the most critical code, such as the kernel code of the operating system; running other relatives than the external privilege ring is not a critical code.
Ø storage system
Any program, the data must be loaded into the main memory, the CPU can operate them, so the operating system itself is also stored in the main memory. 1. The basic knowledge of the memory is divided into a read / write type (RAM: RANDOM Access Memory) and a read-only type (ROM: READ Only Memory) memory, in addition, to simplify the allocation and management of the memory, the memory is divided into blocks, When the user program assigns the main memory space, the block is the minimum unit, so that the block is also referred to as a physical page (PAGE), the size of the block is different with the machine, 512b, 1kb, 4kb, 8kb. (B: Byte computer one byte, one byte = 8 binary positions (bit: bits))
2. The hierarchical capacity, speed, and cost of memory is the main problem considered when the computer storage system design is designed. The typical hierarchical storage architecture is shown: It can be seen that the top layer is smaller, more expensive but fast storage device After the underlying layer is large, the cheaper storage device is subjected to the overall performance of the system to improve the performance of the accessed frequency (most of the case, the accessed frequency is sequentially sequentially register, cache, main memory ...). We know that in the programming technology, we pay attention to the multiplexing of the program code. Once you enter such block code, you will repeat the same instruction set, and there is similar local phenomenon in the memory. , The collection of code and data is maintained in a partial area of a memory over a period of time.
3. Storage Protects data information in the memory where the user program and the operating system must be protected, otherwise it will cause a very serious consequence. Storage protection mainly protects the memory blocks primarily through the interpline register and storage.
Ø Interrupt system
The interrupt refers to the response of the CPU to the asynchronous event that occurs in the system or outside the system. This name is from: When an asynchronous event occurs, the processor is interrupted to the execution of the current program, and turn the processing asynchronous event (interrupt handler) ). For a lightweight example, I am reading, at this time, the phone rang (asynchronous event), so use the book to remember the page (interrupt point) that is watching, then pick up the phone (respond to the asynchronous event and processed), pick up After the phone is complete, continue from the interrupted page (return to the interrupt point execution of the original program). 1. Interrupt: Interrupt can fully utilize the use efficiency and real-time capability of the processor: The input and output devices communicate with the CPU through the interrupt mode to report their data transfer and problems required by the CPU, so that the CPU can immediately run the interrupt handler. At the same time, it also exempts the CPU constant query and waiting, why? It is to know that early CPUs need to pay a lot of time polling in order to pay attention to the I / O status of various input / output devices, now only need to replace by I / O channel or direct storage access (DMA) technology. CPUs are to complete these things (which will be more specifically mentioned later).
2. Several typical interrupts: I / O interrupts, clock interrupts, hardware failure interruptions, programmatic interrupts, system service requests (belong to voluntary interrupts, usually excited by dedicated instructions accessed, for example: x86 processor INT The instruction is interrupted. Generally in the homing state, the voluntary interrupt is intentional arrangement of the operation program, and the other is to compulsive interrupt, which is a running program undesired, typical has a programmed interrupt: arithmetic overflow, Removal, genre program, try to perform illegal nature instructions, access address, etc.)
3. Interrupt system: It is the computer hardware and software to cooperate with each other, which makes the computer system calculate the computational model, and the interrupt system is divided into hardware interrupt device and software interrupt device. The hardware interrupt device is responsible for capturing interrupt requests issued by the interrupt source, and In response to the source, the interrupt handler executes a series of corresponding operations for the interrupt event for a particular interrupt handler. Interrupt system's reception, response, and processing process of interrupt signals, briefly summarizes: receiving and responding to interrupt, protecting interrupt point field, analyzing interrupt vectors, call interrupt handler, interrupt processing end recovery site, the original program continues to execute.
4. Interrupt priority, interrupt shielding and interrupt nested: Now the microprocessor provides multi-level interrupt systems, viewed from hardware, with multiple interrupt requests to connect to interrupt logic from different devices. The interrupt signal is connected to different interrupt request lines, indicating that they have different interrupt levels, and the interrupt level represents the privileged level of the interrupt signal being prioritized, and the interrupt level division is divided according to its emergency and weight, for example, Compared with other interrupt signals, the power-down interrupt signal has a very high priority. In addition, there are two ways to divide priority when there are multiple interrupt signals. Priority, or rotation method: use a table, press the interrupt signal in turn. Interrupt shields are used to allow or disable the response of the interrupt system to some categories interrupts. We know that the interrupt mask is designed in the Program Status Word (PSW), set this shield bit to identify those interrupts or interrupts that are masked. Note: Some interrupt signals cannot be masked, such as machine failure interruptions and power-down, memory parity error, etc. Sometimes, we will encounter an interrupt, which will cause multiple interrupt processing problems. The better processing method is to interrupt nested technology: considering interrupt priority problems, allowing higher priority in interrupt nesters. Interrupt lower priority interrupts. For example, there is a processing when there is a bus, a hard disk, and a scanner three devices in the system. Their interrupt priorities are 9, 5, 3, with a large number of higher priorities. Scan action processing (I / O interrupt of the scanner) starts from a certain time, its processing time has a longer network data transfer request (bus request disruption), at this time, the interrupt of the scanner action processing is required Some of the information on the site performs stack processing, complete the bus service of the network communication, when processing the bus service of the network, submits a request for a hard disk storage file, because the hard disk is not as high as the bus, Delayed, and the priority of the hard disk is higher than the scanner. After completing the bus service of the network communication, the hard disk interrupt process is performed, and then returns to the interrupt handler for the scanner after completion. Ø I / O structure, channel, direct memory access (DMA) technology, buffer technology
The I / O channel involves the I / O channel (interrupt polling of the CPU, increasing the Utilization of the CPU), and its role is also a brief description. Here, it is necessary to emphasize the DMA technology: When the CPU needs to read and write a whole piece of data, it sends a command to the DMA control unit, the command contains the address of the I / O device, start reading or writing the main memory address. , The data length and other information, and the specific data transfer is managed by the DMA controller, and the CPU can deal with other things (enhance the CPU parallel processing capability while increasing the processing I / O performance). Buffer technology is a data staging technique for mitigating a CPU processing data speed and device transmission data speed.
Ø clock
The clock in the computer system is divided into hardware clocks and software clocks, and absolute clocks and relative clocks. The clock can prevent the system from being caught in a dead cycle, and the job is implemented in time, and the correct time signal is given, and the timing wake event determines the event of the time executable.
