Bit Operation Instruction, Processor Control Directive AA. Bit Operation Instruction, 8086 Added set of instructions, including bit test, bit scan. BT, BTC, BTR, BTS, BSF, BSR A.BT (Bit Test), bit test instruction, instruction format: BT OPRD1, OPRD2, Rule: Operation OPRD1 can be a 16-bit or 32-bit general register or storage unit. The operand OPRD2 must be an 8-bit immediate number or a general-purpose register equal to the length of the OPRD1 operator. If you use OPRD2 divided by OPRD1, assume that the merchant is stored in the DIVD, the remainder is stored in the MOD, then the bit number of the OPRD1 operand is MOD, and its main function is to send the value to the test bit to CF, see Several simple examples: B.BTC (Bit Test and Complement), test and reverse usage and rules are the same as BT, but in some different features, it will not only be tested to the value to CF, but also Negate. C.BTR (Bit Test and Reset), the test and reset, the usage and rules are the same as BT, but in some different features, it will not only send the value of the test bit to CF, but also reset this bit (ie 0) . D.BTS (bit test and set), test and set, usage, and rules are the same, but in some different features, it will not only be tested to the value of the value to CF, but also this location (ie 1 1 ). E.BSF (Bit Scan Forward), Bacing Scan, Instruction Format: BSF OPRD1, OPRD2, Function: Scan the OPRD2 operand from right-left (from the lowest bit to highest), and will be the first 1 The bit number is given to the operand OPRD1. Opera OPRD1, OPRD2 can be a 16-bit or 32-bit universal register or a storage unit, but the length of OPRD1 and OPRD2 operands must be equal. F.BSR (Bit Scan Reverse), Reverse Position Scan, Instruction Format: BSR OPRD1, OPRD2, Function: Scan from left-to-right (from the highest bit to the lowest position), and will be 1 The bit number is given to the operand OPRD1. Opera OPRD1, OPRD2 can be 16-bit or 32-bit universal register or storage unit, but the length of OPRD1 and OPRD2 operands must be equal. G. For a simple example to explain these 6 instructions:
AA DW 1234H, 5678H BB DW 9999H, 7777H MOV EAX, 12345678H MOV BX, 9999H BT Eax, 8; CF = 0, EAX remains unchanged BTC EAX, 8; CF = 0, EAX = 12345778H BTR EAX, 8; CF = 0, EAX = 12345678H BTS EAX, 8; CF = 0, EAX = 12345778H BSF AX, BX; AX = 0 BSR AX, BX; AX = 15 Bt Word PTR [AA], 4; CF = 1, [aa] Content constant BTC Word PTR [AA], 4; CF = 1, [aa] = 1223H BTR WORD PTR [AA], 4; CF = 1, [AA] = 1223H BTS Word PTR [AA], 4; CF = 1, [aa] = 1234H BSF Word PTR [AA], BX; [AA] = 0; BSR Word PTR [AA], BX; [AA] = 15 (Decang) BT DWORD PTR [BB], 12; CF = 1, [bb] content remains unchanged BTC DWORD PTR [BB], 12; CF = 1, [BB] = 76779999H BTR DWORD PTR [BB], 12; CF = 1, [BB] = 76779999H BTS DWORD PTR [ BB], 12; CF = 1, [bb] = 77779999H BSF DWORD PTR [BB], 12; [BB] = 0 BSR DWORD PTR [BB], 12; [BB] = 31 (Decang) BB. Processor Control The instruction processor control command is mainly used to set / clear the flag, empty operation, and synchronization with external events. A.CLC, clear the CF logo. B.STC, the CF logo location 1. C.CLI, off interruption. D.STi, open interrupt. E.CLD, Qing DF = 0. F.STD, set DF = 1. G.nop, empty operation, blank area in the procedure, empty operation itself does not perform any operation, mainly for the continuity of the program. H.Wait, waiting for the busy pin. I.lock, the blocking prefix can lock the storage unit of the operand of the instruction, which is always valid during the instruction execution. In multi-task environments, you can use it to ensure exclusive, only the following instructions can be used with LOCK prefix: XCHG, Add, ADC, Inc, Sub, SBB, DEC, NEG, OR, AND, XOR, NOT, BT , BTS, BTR, BTC J. Description Processor Type Dialog. 8086, only support assembly of 8086 instructions. 186, only support assembly of 80186 instructions. 286, support assembly of non-privileged 80286 instructions. 286c, Support for assembly of non-privileged 80286 instructions. Support for compilation of 80286 all instructions. 386, support assembly of 80386 non-privileged instructions. 386c, support assembly of 80386 non-privileged instructions. 386p, support for all instructions to 80386 Compilation Only the processor type is used to illustrate the processor type, and the assembler knows how to better compile, connect programs, and better detect the error. In the subsequent sever, the 80386 segment page management mechanism and control register, debug register, and how to program in 386 real-mode and protection mode.
