Arithmetic operation instructions, logical operation instructions, shift command AA. Arithmetic operations ADD, ADC, INC, SUB, SBB, DEC, CMP, NEG A.ADD, and 8086 function, same, but support 32-bit operation, the following statement is legal. Add ESI, EDI Add Eax, DWORD PTR [1000H] B.Adc, carrying addition instruction, ie OPRDS OPRDD CF, where oprds represents the source operand, OPRDD represents the purpose of the purpose, CF represents the carry flag, function and usage and 8086 Support 32-bit operations. C.SUB, and 8086, support 32-bit operations. D.SBB, with carry of subtracted command, OPRDD-OPRDS-CF, where OPRDS represents the source operand, OPRDD represents the operand, and the CF represents the carry flag, function and usage is the same as 8086, and supports 32-bit operations. E.DEC, minus 1 operation, function and usage are the same as 8086, support 32-bit operations. F.cmp, comparison operations, functions, and usage are the same as 8086, support 32-bit operations. G. NG, the function, function and usage are the same as 8086, support 32-bit operations. H.inca 1 operation, function and usage are the same as 8086, support 32-bit operations. B. Multiple Method Directive MUL, DIV, IMUL, IDIV A.mul, No Symbol Multiplication Directive, and 8086 Function Usage, that is, only one operation is given in the instruction, and the multiplier has been default, if the number of operands given by the instruction If 32, the multiplication is default EAX, then the product will be stored in EDX: EAX, where EDX is 32 digits, and EAX is stored low. If EDX = 0, the high 32 bit is 0, Then = 0, CF = 0, otherwise it is set. If the number of figures given by the instructions is 16-bit, the multiplication is default that AX will be placed in DX: AX, where the DX is 16 bits, and AX is stored in 16 bits. If the number of operands given by the instruction is 8 bits, the multiplication is deflated by default, then the product will be placed in AX, and the AH is stored in 8 bits, and the AL is stored in 8 bits. B. Div, unsigned number of division instructions, like 8086, the instruction gives an operand, and the divisor has been default. If the operand given in the instruction is 32, the divided number will be EDX: EAX, and the final business will be stored in Eax, and the remainder will be stored in EDX. If the instruction gives an operand to 16 bits, then the divided amount is EAX, the finally obtained is discred in AX, the remainder is in the high 16 bits of EAX. If the number given in the instruction is 8 bits, the divided is 16 bits, and the final result will be placed in Al, the remainder is placed in AH. C. Imul, a multiplication of symbols, in addition to the use of 8086, there is a new form: C1.Imul DST, SRC; multiplied the source operand SRC with the purpose of operation DST, and send the result to the DST. C2.Imul DST, SRC1, SRC2; multiplied the source operand SRC1 with the source operand SRC2, and send the result to the DST.
Using this form must be observed, the purpose of the destination operand in the form C1 command must be a 16-bit or 32-bit register, and the length of the source operand must be the same as the length of the target operation (8-bit immediate count, ie 00h-ffh or 80H-7FH), the source operand can be a general register or a storage unit or immediately. The source operand SRC1 in the form C2 command can be a general purpose register or a storage unit, and the source operand SRC2 must be an immediate number, and the DST must be a 16-bit or 32-bit universal register. Oh, no need to ask for these rules, this is the characteristic of hardware, if you must ask why, you can only ask Intel's hardware engineers :). At the same time, there is a point to pay attention to: these two forms of instructions, the length of the destination register is the same as the length of the source, except for the first number of times), in this way, the instruction is in fact the number of symbols and unsigned numbers The same, because the low portion of the product is stored in the destination register, and the high portion is not stored in these two forms of instructions. D.IDIV, the division of the symbol number, the same, and 8086, but support 32-bit operations. C. Symbol Extended Directive CBW, CWD, CWDE, CDQ A.CBW, in the foregoing, in the third article. B.CWD, in the previous introduction, in the third. C. CWDE is an 80386 new instruction. Format: CWDE. Function: Extend the AX symbol bits to the EAX high 16 bits. D. CDQ is an 80386 new instruction. Format: CDQ. Function, extend EAX's symbolic bits into EDX. E. The above four instructions do not affect the marker. F. Example:; if AX = 1234H, EAX = 99991234H CBW; after processing the instruction, AX = 1234, DX = 0000H cdq; after processing the instruction, ED = 99991234H, EDX = fffffffh
BB. Logical Operation Instructions and Shift Instructions NOT, AND, OR, XOR, TEST, SAL, SAR, SHL, SHR, ROL, ROR, RCL, RCR, SHLD, SHRD A.NOT, AND,, OR, XOR, TEST The functionality and usage of the instruction is identical to 8086, but they support 32-bit operations. B. Test, test instruction, the result of this instruction test does not return to the destination operand and source number. The reason why this one is used, mainly because of the results obtained according to the TEST instruction, the program is transferred. C.SAL, arithmetic left shift, functionality and 8086, but in 8086, if the number of bits in shift exceeds 1 bit, then the number of bits to be shifted is placed in the CX register. In 80386, you can do this, and other shift instructions are the same. In addition to this, 32-bit operations are also supported by usage and 8086. The following statements are legal. SHL Al, 5; this is illegal in 8086, but is a legal SHL Word PTR [Si], 3 D.SAR, the right movement in 80386, and the number of digits of the number of operands, but the sign bit on the left Keep the minimum position that removes into the CF flag. E.SHL, logical left shift, usage and function are the same as SAL. F.SHR, logic right shift, turn right to right, at the same time, each shift one bit, 10 supplements on the left, the minimum bit into the CF flag. g. Description: In 80386, the actual shift bit is 5 digits of the number of shift bits in the instruction, which means that the number of shift bits is 0-31 or 0-1FH, and the CF flag is always retained. The destination operand is finally removed. When the number of shift bits is greater than the length of the operand, the CF is set 0. If the number of shift bits is 1, the symbol bits of the result before and after the shift are the same, then it is obvious that the operand is not removed after shifting, and OF = 0. The displacement schematic diagram of these four instructions (I painted the 16-bit operation shift schematic, 8-bit and 32 in this class), SAL, SHL equivalent to multiplication; SAR, SHR is equivalent to division.
Sal: | ----------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------- | | CF | < | BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | Bit10 | Bit9 | Bit8 | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | | - -------------- -------------------------------------------------- ------------------------ | SHL: | ------------------------------------------------------------------------------------------------ -------------------------------------------------- ------------------- | | CF | <- | bit15 | bit14 | bit13 | bit12 | bit11 | bit10 | bit9 | bit8 | bit7 | bit6 | bit5 | bit4 | Bit3 | Bit2 | Bit1 | Bit0 | | --- ---------------------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------- | SAR: | ----------------------------------------------- --------------------------------------------- | | - | bit15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | Bit9 | Bit8 | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | -> | CF || | | --- | ------- -------------------------------------------------- ------------------------------- | | ^ | ----- | The highest bit remains the same shr: | -------------------------------------------------- -------------------------------- --------- | 0-> | BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | Bit10 | Bit9 | Bit8 | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | -> | | CF || | ------------------------------------------------------------------------------------------------------------------------- --------------------------------------------- | H. Rol, The loop left shift, support 32-bit operands, usage and 8086. I.ror, loop right shift, support 32-bit operands, usage and 8086. J.RCL, with the carry cycle left shift, support 32-bit operands, usage and 8086. K.RCR, with carry cycle right shift, support 32-bit operands, usage and 8086.
L. ROM, ROR, RCL, RCR shift (still drawn by 16-bit operands, 8-bit / 32 digits): rol: | --------------- -------------------------------------------------- --------------------------------- | | <- | bit15 | bit14 | bit13 | bit12 | bit11 | bit10 | Bit9 | Bit8 | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | ---------------------------------------------------------------------------------------------- -------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------- ----------------------------- | Ror: | ----------------- -------------------------------------------------- ------------------------ | | -> | BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | Bit10 | Bit9 | Bit8 | Bit7 | Bit6 | Bit5 | BIT4 | BIT3 | Bit2 | Bit1 | Bit0 | -> | | ---------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------- ------ | | ---------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------- | RCL: | ----------------------------------------------- -------------------------------------------------- | | <- | cf | <- | bit15 | bit14 | bit13 | bi T12 | BIT11 | BIT10 | Bit9 | Bit8 | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | <- | | ------------------------------------------------------------------------------------ -------------------------------------------------- ----------------------------------------------------- -------------------------------------------------- -------------------------- | RCR: | -------------------- -------------------------------------------------- --------------------------- | | -> | cf | <- | bit15 | bit14 | bit13 | bit12 | bit11 | bit10 | bit9 | Bit8 | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 | -> | | ------------------------- -------------------------------------------------- ------------------- | | ----------------------------- -------------------------------------------------- ------------------ | M.SHLD,
80386 new double precision left instruction, instruction format: SHLD OPRD1, OPRD2, M n.shrd, 80386 Added double precision right shift instruction, instruction format: SHRD, OPRD1, OPRD2, M om, n these two instructions The use rule is: source operation OPRD1 can be a 16-bit or 32-bit general register or a 16-bit storage unit or a 32-bit storage unit, and the source operand OPRD2 must be a 16-bit or 32-bit register, m represents the number of shifts, can It is a CL register or 8 bits immediately. Function: SHLD is to move the source OPRD1 M-bit, the empty bit is fill the M bits of the OPRD2 high-end M bits, the content of the source operand OPRD2 is constant, and the last shift is placed in CF; SHRD will operate OPRD1 Move the M bit, the empty bit is filled with the OPRD2 low-end M bits, and the source operand OPRD2 remains unchanged. The last shift is placed in the CF. For these two instructions, when the number of shift bits is only 1, When the symbolic position is removed, then OF = 0, if the symbol bit is different, that of = 1. p. These two instructions are 80386 new instructions, and two simple examples are explained: p1.shld: MOV AX, 8321H MOV DX, 5678H SHLD AX, DX, 1 SHLD AX, DX, 2 analysis of this directive Detailed execution process (with schematic, the first picture is AX content): AX = 8321h | --------------------------- ---- | | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | | ----------- -------------------- | According to the command shld AX, DX, 1, first left, get AX = 0642h: | -------- ----------------------- | | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | CF = 1 | ------------------------------- | After the last step is shifted The last bit (ie, bit0) of AX is empty, its value is 0; according to the order of the instruction will be filled with DX, the contents of AX after filling are: | ----------- -------------------- | | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The symbolic bit of the AX is different, so it produces overflow during shift, OF = 1, the last result AX = 0642H.
