80386 ASM program design foundation, huh, this is my hobby in my hobby recently. This issue will continue to launch a number of 80386ASM programming, mainly introducing the detailed usage of 80386ASM instructions and how to program the virtual 8086 mode programming in 80386, and I will detail the segment page management mechanism under 80386. I will compare the instructions under 80386 with the same instructions under 8086. Before you look at Luo Yunbin's ASM programming, you may wish to look at my basic articles first, I hope to be a friend who is engaged in assembly language and adds more comments.
The 80386 processor is a milestone in the history of Intel's 80x86 development. It is not only compatible with the previous 8086/8088, 80186, 80286 processor, but also has made solid Basics, more importantly, what are our programs, what extensions are concerned about 80386 in the instructions? What are the addressing methods of 80386? There is no doubt that it is not only compatible with all of the 8086 instructions, but also enhances them.
Oh, I know that there are many people asking me that the CPU has developed to Pentiumiii, there is no need to learn 80386 assembly. In fact, the protection mode of the 80386 processor, the virtual 8086 mode, and the segment page management mechanism of the address, the virtual memory is the core of the later processor. Therefore, 80386 is the foundation of the subsequent development processor, such as 80486 substantially 80386 80387 coordinating, this coprocessor is mainly used to handle floating point operations, and the Pentium processor adds 57 instructions on the basis of 80386 instructions. 8 data types, 8 64-bit registers to handle multimedia. From this point of view, it is necessary to know 80386ASM, which seems to learn 80386, and must first master 8086.
1.80386 registers:
80386 registers can be divided into 8 groups: universal registers, segment registers, command pointer registers, flag registers, system address registers, control registers, debug registers, test registers, their widths are 32 bits. This article mainly introduces the 80386 register.
A1.General Register (universal register)
EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP, their low 16 bits are 8086 AX, BX, CX, DX, Si, Di, SP, BP, and their meanings are as follows:
EAX: accumulator
EBX: base register
ECX: Counter
EDX: Data Register
ESI: source address pointer register
EDI: Destination address pointer register
EBP: base pointer register
ESP: Stack Pointer Register
These registers can be accessed separately from 16-bit, that is, 8086 AX, BX, CX, DX, Si, Di, SP, BP, in accessing these registers (AX, BX, CX, DX, Si) , Di, SP, BP), it
The high 16 bits are unaffected, while the four registers of AX, BX, CX, and DX are as follows, and they can be alone (AH, Al, BH, BL, CH, CL, DH, DL)
A2: segment register (segment register)
In addition to the 4 sections of 8086 (CS, DS, ES, SS), 80386 also increased two segments FS, GS, which are 16-bit, and their meaning is as follows:
CS: Code Segment
DS: Data Section (Data Segment)
ES: Additional Data Section (EXTRA Segment)
SS: Stack Segment
FS: Additional Section GS Addition Section
A3: Instruction Pointer (instruction pointer register)
EIP, its low 16 bits is the 8086 IP, which stores the next address to perform the instruction.
A4: Flag Register (Sign Register)
Compared with the 16-bit flag register of EFLAGS, and 8086, it adds to four control bits, but these four control bits they don't work in real-mode, these four control bits are:
A.iopl (I / O Privilege Level), I / O Privilege Level Field, its width is 2bit, which specifies the privilege level of the I / O instruction. If the current privilege level is less than or equal to IOPL, the I / O command can be executed. Otherwise, a protective exception will occur.
B.NT (NESTED TASK): Control Interrupt Returns IRET, which is 1 bit. NT = 0, restore EFLAGS, CS, and EIP to the value saved in the stack to implement the interrupt return; NT = 1, then the interrupt is turned back by task switching.
C.RF (RESTART FLAG): Restart the flag, which is 1 bit. It mainly controls whether to accept debug faults. Rf = 0 accepts, RF = 1 ignores. If each of your programs is successfully executed, then RF will be cleared 0. When a non-debug fault is accepted, the processor sets RF = 1.
D.VM (Virtual Machine): Virtual 8086 mode (using software to simulate 8086 mode, "also known as virtual machine). VM = 0, the processor works in general protection mode; VM = 1, working in V8086 mode.
The meaning of 16 other signatures is the same as 8086, and it is also revoked here:
E.cf (carry flag): carry flag, controlled by the CLC, STC two flags
F.PF (Parity Flag): parity flag
G.af (Assistant Flag): Auxiliary Ground Sign
H.zf (Zero Flag): Zero Log
I.SF (Singal Flag): Symbol Sign
J.IF (Interrupt Flag): Interrupt Allow flag, controlled by two instructions by CLI, STI
K.DF (Direction Flag): Vector flag, controlled two instructions by CLD, STD
L.OF (Overflow Flag): Overflow flag.
Control registers, system address registers, debug registers, and test registers will be introduced after the 80386 segmentation and page management mechanisms, please continue to pay attention to the second "80386 memory addressing method".
