Makefile writing
When you start using Linux programming, a very annoying question is how to write the makefile file, because it is not as familiar with Windows under Linux, there is so much good software (maybe it is lonely for Linux). Although the integrated compilation environment like Kylix and Anjuta, Kylix is too slow, using the console program is not as high as a high-tech gun mosquito - large materials, and Anjuta is too unstable, and the font is so ugly. Don't say it, or just right, see how Makefile should write.
1. Simple GCC syntax:
If you have only one file (or only a few files), you can use the GCC directly to compile the Makefile file (of course Makefile more convenient). Here we only introduce a few parameters I often use, the first is "-o", which is the target file to be output, and then "-c", indicating only compiling (Compile), no Connection (Make), if there is no "-c" parameter, then it means a connection, such as the following command:
GCC -C Test.c, indicating that only the Test.c file, output the target file Test.o when successful
GCC-C Test.c -o test.o, identical to the previous order
GCC -O Test Test.o, connect Test.o into executable binary TEST
GCC -O Test Test.c, compile Test.c and connected to the executable binary TEST
GCC Test.c -o test, same as the previous command
GCC-C Test1.c, only compile TEST1.C, output the target file TEST1.O when successful
GCC-C Test2.c, only compile TEST2.C, output target files Test2.o when successful
GCC -O Test Test1.o Test2.o, connect TEST1.O and TEST2.O to executable binary TEST
GCC -C Test Test1.c Test2.c, compile TEST1.O and TEST2.O and connected to executable binary TEST
Note: If you want to compile CPP files, use G , otherwise there will be a inexplicable error similar to the following:
CC3R3i2u.o (.eh_frame 0x12): undefined reference to `__gxx_personality_v0 '...
There is also a parameter is "-l" parameter, which is connected to the link library to indicate the connection, such as multi-thread, if you use the pthread_create function, then you should add the last plus "" - LPTHREAD "," - l "means connection," pthread "means the library to connect, pay attention to them here, and if you use the optical label Curses, then you should add" -lcurses ", Such as the following:
GCC -O Test Test1.o Test2.o -lpthread -lcurses
Of course, I feel hundreds of GCC's parameters, but we usually use it in the X86 machine, and this is not a GCC tutorial here, so this will stop.
2. Makefile Basic Law
I have a detailed design book here, just make some simple introduction with someone's makefile files and some online references (I understand it yourself, I will ask everyone to point out, the monks will not be grateful 2.1 Goals:
Everyone is sure to see someone used Makefile files, and there are often orders that use Make All, make install, make clean, and only one makefile file, then how is all, install, how is the Makefile file (this There is a problem, but I don't know what to say, everyone can understand what I mean, let me put me a horse)? Here, if you can run it correctly, if you can run correctly, then there must be such a line in the Makefile file, and their start must be
All: ×××××××××
××××××××××××××
INSTALL: ×××××××
××××××××××××××
Clean: ××××××××××
××××××××××××××
Of course, not, because all, install, clean we can use other variables instead, but we have simply sought, and you will be unworthy.
The all, install, clean, etc. mentioned above is the goal we say. Make all command tells Make We will perform the target specified by all. In order to facilitate understanding the process of the Make program, we will give you a Makefile file that is unrelated to GCC:
# # # 表示 mf 的 注,, below is the specific content of the makefile file
All:
@echo you have type type command "make all"
Clean:
@echo you have used command "make clean"
INSTALL:
@EHCO you have used command "Make $ @"
#Makefile file end
Note here, all:, clean:, install: Direction, and all @echo, it is necessary to add a Tab key to easily. Below is the result:
[root @ xxx test] #cat makefile
# # # 表示 mf 的 注,, below is the specific content of the makefile file
All:
@echo you have type type command "make all"
Clean:
@echo you have used command "make clean"
INSTALL:
@EHCO you have used command "Make $ @"
[root @ xxx test] #make all
You have used command "make all"
[root @ xxx test] #make clean
You have used command "make clean"
[root @ xxx test] #make install
You have used command "make install"
[root @ xxx test] #
I don't know if you don't know that there is a symbol $ @, where $ represents the variable name in the makefile file, and it is to explain as a variable, $ @ is the Makefile pre-defined variable, indicating the target command, for example The file belongs to the install target, then $ @ means install, similarly, if you exchange the "make Clean" of the plus number below: "Make $ @", then the output of Make Clean is originally a touch the same. You can try it out. 2.2 dependence
We now put forward such a question: How do I use a make command to replace all make all, make install, make clean? Of course we can write a Makefile file like just now:
[root @ xxx test] #cat makefile
# # # 表示 mf 的 注,, below is the specific content of the makefile file
All:
@echo you have type type command "make all"
Clean:
@echo you have used command "make clean"
INSTALL:
@EHCO you have used command "Make $ @"
DOALL:
@echo you have used command "Make $ @ L"
@echo you have type type command "make all"
@echo you have used command "make clean"
@EHCO you have useted command "make install"
[root @ xxx test] #make doall
You have used command "make doall"
You have used command "make all"
You have used command "make clean"
You have used command "make install"
[root @ xxx test] #
Here, doall: The target has 4 adjustment, they all start with the Tab key. Of course, this is able to complete the task, but it's too stupid, let's write like this:
[root @ xxx test] #cat makefile
# # # 表示 mf 的 注,, below is the specific content of the makefile file
All:
@echo you have type type command "make all"
Clean:
@echo you have used command "make clean"
INSTALL:
@EHCO you have used command "Make $ @"
DOALL: All Clean INSTALL
@echo you have used command "Make $ @ L"
[root @ xxx test] #make doall
You have used command "make all"
You have used command "make clean"
You have used command "make install"
You have used command "make doall"
[root @ xxx test] #
I believe that everyone has already seen the DOALL: running method, which runs the ALL target and runs the Clean target, then INSTALL, and finally the target of its own itself, and each $ @ still maintains its respective target name. Here, we call all, clean, install as the goal depends on DOALL, referred to as DOALL dependence. That is, you have to execute DOALL, please perform them (all, clean, install), and finally perform my code.
Pay attention to dependence, it is the goal inside Makefile, otherwise you have to run, the ending is destined:
[root @ xxx test] #cat makefile
All:
@echo you have type type command "make all"
XXX: All Wahaha:
[root @ xxx test] make xxx
You have used command "make all"
Make: *** no rule to make target 'wahaha', needed by `xxx ', STOP.
[Easy] Can we make "mutual dependence" to make Make?
[root @ xxx test] #cat makefile
TAR1: TAR2
TAR2: TAR1
@echo this line cann't be shown on you screen!
[root @ xxx test] make Tar1
Circular Tar2 <- TAR1 Dependency Dropped.
Oh, I can't swindle.
3. Actual combat:
With the above instructions, we can start writing some kind of Makefile files. For example, we have the following documents:
TMP /
-- Include /
| ---- f1.h
| ---- f2.h
---- f1.c
---- f2.c
- main.c
Wheref1.c #include "incrude / f1.h", f2.c #include "incrude / f2.h", main.c and #include "incrude / f1.h", #include "include / f2 .h ", the main function is in main.c, to combine they to compile as the target for TestMF, we can write it below (of course we are mentally):
[root @ xxx test] #cat makefile
Main: main.o f1.o f2.o
GCC -O Testmf main.o f1.o f2.o
F1.O: f1.c
gcc -c -o file1.o file1.c
F2.O: f2.c
gcc -c -o file2.o file2.c
Main.o
gcc -c -o main.o main.c
Clean:
Rm -Rf f1.o f2.o main.o testmf
[root @ xxx test] make
gcc -c -o main.o main.c
gcc -c -o file1.o file1.c
gcc -c -o file2.o file2.c
GCC -O Testmf main.o f1.o f2.o
[root @ xxx test] LS
F1.c f1.o f2.c f2.o main.c main.o include / testmf
If your program is no problem, it should be executed ./testmf
