Recently, a CPU's information should be organized, it should be more comprehensive.
Almost now all X86 CPUs have built-in CPUID instructions to distinguish between authenticity, some CPU vendors such as AMD, VIA, etc. also have built-in multi-extension CPUID instructions, which is more convenient.
Below we use Delphi to implement a CPU detection software.
The CPUID is as follows:
ASM
Push EAX
Push EBX
Push ECX
Push Edx
Mov Eax, X
// ******************************************************** ******
// CPUID instruction, because Delphi's assembly compiler does not have built-in instructions,
// So use the instrument language code of this command $ 0f, $ A2 to implement
// ******************************************************** ******
DB $ 0F, $ A2
POP EDX
POP ECX
POP EBX
POP EAX
END;
The parameter of the CPUID instruction is Eax, Mov Eax, x This sentence is to assign X to Eax.
The returned parameters are stored in EAX, EBX, ECX, and EDX.
We can write a function:
Type
TCPUIDRESULT = Record
Eax: DWORD;
EBX: DWORD;
ECX: DWORD;
EDX: DWORD;
END;
......
Function CPUID (EAX: DWORD): TCPUIDRESULT;
ASM
Push EAX
Push EBX
Push ECX
Push Edx
Mov Eax, EAX
// ******************************************************** ******
// CPUID instruction, because Delphi's assembly compiler does not have built-in instructions,
// So use the instrument language code of this command $ 0f, $ A2 to implement
// ******************************************************** ******
DB $ 0F, $ A2
Mov Result.eax, EAX
Mov Result.ebx, EBX
Mov Result.ecx, ECX
Mov Result.edX, EDX
POP EDX
POP ECX
POP EBX
POP EAX
END;
CPUID parameter and return value list:
EAX = 0000_0000h
Enter EAX = 0000_0000H to get the maximum value supported by the CPUID instruction and the name string of the manufacturer
Output eax = xxxx_xxxx gets the maximum value supported by the CPUID instruction # 1
EBX-EDX-ECX manufacturers Name string # 2
GenuineIntel Intel processor
UMC UMC UMC UMC Processor
Authenticamd AMD processor
Cyrixinstead Cyrix processor
Nexgendriven NexGen processor
CENTAURHAULS CENTAUR processor
RISERISERISE RISE TECHNOLOGY processor
Genuinetmx86 Transmeta processor
Geode by NSC National Semiconductor Processor
Description description
# 1 pre-b0 STEP INTEL P5 processor returns EAX = 0000_05XXH.
# 2 Pre-B0 Step Intel P5 processor cannot return to the vendor string
EAX = 0000_0001h
Enter EAX = 0000_0001H to get the processor type / family / model / stepping and the appearance identity
Output EAX = xxxx_xxxxh processor Type / Family / Model / SteppINGextended Family Extended Family is BITS 27..20.
00h Intel P4
01H Intel Itanium 2 (IA-64)
Extended Model Extended Model is BITS 19..16.
Type Type is Bit 13 and Bit 12.
11b reserved
10b second block processor
01b Overdrive processor
00b first processor
Family family is BITS 11..8.
4 MOST 80486S
AMD 5x86
Cyrix 5x86
5 Intel P5, P54C, P55C, P24T
NexGen NX586
Cyrix m1
AMD K5, K6
Centaur C6, C2, C3
Rise MP6
Transmeta Crusoe TM3X00 and TM5x00
6 Intel P6, P2, P3
AMD K7
Cyrix M2, VIA Cyrix III
7 Intel Itanium (IA-64)
F If you are this value, you will see Extended Family.
Model Model is BITS 7..4.
Intel F If you are this value, you will see Extended Model.
Intel 80486 0 I80486DX-25/33
1 I80486DX-50
2 I80486SX
3 I80486DX2
4 I80486SL
5 I80486SX2
7 I80486DX2WB
8 I80486DX4
9 I80486DX4WB
UMC 80486 1 U5D
2 U5S
AMD 80486 3 80486DX2
7 80486DX2WB
880486DX4
9 80486DX4WB
E 5x86
F 5x86WB
Cyrix 5x86 9 5x86
Cyrix Mediagx 4 GX, GXM
Intel P5-Core 0 P5 A-STEP
1 p5
2 p54c
3 p24t overdrive
4 p55c
7 p54c
8 p55c (0.25μm)
NEXGEN NX586 0 NX586 or NX586FPU (Only Later ")
CYRIX M1 2 6x86
CYRIX M2 0 6x86mx
VIA Cyrix III 5 Cyrix M2 Core
6 Winchip C5a Core
7 Winchip C5B Core (if Stepping = 0..7)
7 Winchip C5C Core (if Stepping = 8..f)
8 Winchip C5C-T Core (if Stepping = 0..7)
AMD K5 0 SSA5 (PR75, PR90, PR100)
1 5k86 (PR120, PR133)
2 5k86 (PR166)
3 5k86 (PR200)
AMD K6 6 K6 (0.30 μm)
7 k6 (0.25 μm)
8 k6-2
9 K6-III
D K6-2 or K6-III (0.18 μm)
Centaur 4 C6
8 C2
9 C3
RISE 0 MP6 (0.25 μm)
2 mp6 (0.18 μm)
Transmeta 4 Crusoe TM3X00 and TM5X00
Intel P6-Core 0 P6 A-STEP
1 p6
3 p2 (0.28 μm)
5 p2 (0.25 μm)
6 p2 WITH ON-DIE L2 Cache7 P3 (0.25 μm)
8 p3 (0.18 μm)
WITH 256 KB ON-DIE L2 CACHE
A p3 (0.18 μm)
With 1 or 2 MB on-Die L2 Cache
B P3 (0.13 μm)
WITH 256 or 512 KB ON-DIE L2 CACHE
AMD K7 1 Athlon (0.25 μm)
2 Athlon (0.18 μm)
3 DURON (sf core)
4 Athlon (TB Core)
6 Athlon (PM Core)
7 DURON (MG Core)
8 Athlon (TH Core)
A athlon (Barton core)
Intel P4-Core 0 P4 (0.18 μm)
1 p4 (0.18 μm)
2 p4 (0.13 μm)
3 p4 (0.09 μm)
Stepping stepping in BITS 3..0.
Stepping describes the details of the processor.
EBX = aall_ccbbh brand ID BRAND ID is 7..0.
00h does not support
01H 0.18 μM Intel Celeron
02H 0.18 μM Intel Pentium III
03H 0.18 μM Intel Pentium III Xeon
03H 0.13 μM Intel Celeron
04H 0.13 μM Intel Pentium III
07h 0.13 μM Intel Celeron Mobile
06H 0.13 μM Intel Pentium III Mobile
0AH 0.18 μM Intel Celeron 4
08h 0.18 μM Intel Pentium 4
09H 0.13 μM Intel Pentium 4
0EH 0.18 μM Intel Pentium 4 Xeon
0BH 0.18 μM Intel Pentium 4 Xeon MP
0bh 0.13 μM Intel Pentium 4 Xeon
0CH 0.13 μM Intel Pentium 4 Xeon MP
08H 0.13 μM Intel Celeron 4 Mobile
0EH 0.13 μM Intel Pentium 4 Mobile (Production)
0FH 0.13 μM Intel Pentium 4 Mobile (Samples)
CLFLUSH CLFLUSH (8-Byte) in Bits 15..8.
CPU Count Logic Processor Quantity BITS 23..16.
APIC ID default (fixed) APIC ID is BITS 31..24.
ECX = XXXX_XXXXH Feature Flags Description
BITS 31 ... 11 Reserved
Bit 10 (CID) Context ID: L1 data cache can be set to adapt or sharing mode
Bit 9 Reserved
Bit 8 (TM2) Cat Monitor 2
Bit 7 Reserved
Bit 6 Reserved
Bit 5 Reserved
Bit 4 (DSCPL) CPL-Qualified Debug Store
Bit 3 (Mon) Monitor
Bit 2 Reserved
Bit 1 Reserved
Bit 0 (SSE3) SSE3, MXCSR, CR4.OSXMMEXCPT, #xf, if FPU = 1 also supports fisttp
EDX = XXXX_XXXXH Fight Sign Description
Bit 31 (PBE) Pending Break Event, Stpclk, Ferr #, MISC_ENABLE MSR
BIT 30 (IA-64) IA-64
Bit 29 (TM) Therm_Interrupt, Therm_status, and Misc_enable msrsxapic thermal lvt entrybit 28 (htt) Hyper-Threading Technology
Bit 27 (SS) SelfSnoop
Bit 26 (SSE2) SSE2, MXCSR, CR4.OSXMMEXCPT, #XF
Bit 25 (SSE) SSE, MXCSR, CR4.OSXMMEXCPT, #xf
Bit 24 (FXSR) FXSAVE / FXRSTOR, CR4.OSFXSR
Bit 23 (mmx) MMX
Bit 22 (ACPI) Therm_Control MSR
Bit 21 (dtes) Debug TRACE AND EMON Store MSRS
Bit 20 reserved
Bit 19 (CLFL) CLFLUSH
Bit 18 (PSN) PSN (See Standard Eax = l 0000_0003H), PSN_DISABLE MSR # 1
Bit 17 (PSE36) 4 MB PDE BITS 16..13, Cr4.pse
Bit 16 (PAT) PAT MSR, PDE / PTE.PAT
Bit 15 (CMOV) CMOVCC, IF FPU = 1 THEN Also Fcmovcc / F (U) COMI (P)
BIT 14 (MCA) MCG _ * / MCN_ * MSRS, CR4.MCE, #MC
Bit 13 (PGE) PDE / PTE.g, Cr4.pge
Bit 12 (mtrr) mtrr * msrs
Bit 11 (SEP) SYSENTER / SYSEXIT, SEP_ * MSRS # 2
Bit 10 reserved
Bit 9 (APIC) APIC # 3, # 4
Bit 8 (CX8) CMPXCHG8B # 5
Bit 7 (MCE) MCAR / MCTR MSRS, CR4.MCE, #MC
Bit 6 (PAE) 64bit PDPTE / PDE / PTES, CR4.PAE
Bit 5 (MSR) MSRS, RDMSR / WRMSR
Bit 4 (TSC) TSC, RDTSC, CR4.TSD (Doesn't Imply MSR = 1)
Bit 3 (PSE) PDE.ps, PDE / PTE.RES, CR4.PSE, #PF (1xxxb)
Bit 2 (de) cr4.de, dr7.rw = 10b, #ud on mov from / to DR4 / 5
Bit 1 (VME) CR4.VME / PVI, EFLAGS.VIP/VIF, TSS32.IRB
Bit 0 (FPU) FPU
Description
# 1 If the PSN invalid PSN appearance is 0.
# 2 Although the Intel P6 processor does not support SEP, it is still false here (I really don't know what Intel thinks).
# 3 APIC is invalid, then the APIC looks sign is 0.
# 4 Early AMD K5 Processor (SSA5) will support the PGE.
# 5 The processor does support CMPXCHG8B but the default is the report is not supported. In fact, this is a bug of Windows NT.
EAX = 0000_0002h
Enter EAX = 0000_0002H to get a processor configuration description
Output EAX.15..8
EAX.23..16
EAX.31..24
EBX.0..7
EBX.15..8
EBX.23..16
EBX.31..24
ECX.0..7
ECX.15..8
ECX.23..16
ECX.31..24
EDX.0..7
EDX.15..8
EDX.23..16
EDX.31..24 configuration description
Value description
00h null descriptor (= unused descriptor) 01H Code TLB, 4K Pages, 4 Ways, 32 Entries
02H Code TLB, 4M Pages, Fully, 2 Entries
03H Data TLB, 4K Pages, 4 WAYS, 64 Entries
04H Data TLB, 4M Pages, 4 WAYS, 8 Entries
06H Code L1 Cache, 8 KB, 4 WAYS, 32 BYTE LINES
08H Code L1 Cache, 16 KB, 4 WAYS, 32 BYTE LINES
0ah Data L1 Cache, 8 KB, 2 WAYS, 32 BYTE LINES
0CH Data L1 Cache, 16 KB, 4 WAYS, 32 BYTE LINES
10h Data L1 Cache, 16 KB, 4 WAYS, 32 BYTE LINES (IA-64)
15h Code L1 Cache, 16 KB, 4 WAYS, 32 BYTE LINES (IA-64)
1AH Code and Data L2 Cache, 96 KB, 6 Ways, 64 BYTE LINES (IA-64)
22H Code and Data L3 Cache, 512 KB, 4 Ways (!), 64 BYTE LINES, DUAL-SECTORED
23H Code and Data L3 Cache, 1024 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED
25H Code and Data L3 Cache, 2048 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED
29H Code and Data L3 Cache, 4096 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED
39H Code and Data L2 Cache, 128 KB, 4 Ways, 64 Byte Lines, Sectored
3BH Code and Data L2 Cache, 128 KB, 2 Ways, 64 Byte Lines, Sectored
3CH Code and Data L2 Cache, 256 KB, 4 Ways, 64 Byte Lines, Sectored
40h no integrated L2 Cache (P6 Core) Or L3 Cache (P4 CORE)
41H Code and Data L2 Cache, 128 KB, 4 WAYS, 32 BYTE LINES
42H Code and Data L2 Cache, 256 KB, 4 Ways, 32 Byte Lines
43H Code and Data L2 Cache, 512 KB, 4 WAYS, 32 BYTE LINES
44H Code and Data L2 Cache, 1024 KB, 4 WAYS, 32 BYTE LINES
45H Code and Data L2 Cache, 2048 KB, 4 WAYS, 32 BYTE LINES
50H Code TLB, 4K / 4M / 2M Pages, Fully, 64 Entries
51H Code TLB, 4K / 4M / 2M Pages, Fully, 128 Entries
52H Code TLB, 4K / 4M / 2M Pages, Fully, 256 Entries
5bh Data TLB, 4K / 4M Pages, Fully, 64 Entries
5CH Data TLB, 4K / 4M Pages, Fully, 128 Entries
5DH Data TLB, 4K / 4M Pages, Fully, 256 Entries66h Data L1 Cache, 8 KB, 4 WAYS, 64 BYTE LINES, SECTORED
67h Data L1 Cache, 16 KB, 4 WAYS, 64 BYTE LINES, SECTORED
68H Data L1 Cache, 32 KB, 4 WAYS, 64 BYTE LINES, SECTORED
70H TRACE L1 Cache, 12 KμOps, 8 Ways
71H TRACE L1 Cache, 16 kμops, 8 Ways
72H TRACE L1 Cache, 32 k μOps, 8 Ways
77H Code L1 Cache, 16 KB, 4 WAYS, 64 BYTE LINES, SECTORED (IA-64)
79H Code and Data L2 Cache, 128 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED
7AH Code and Data L2 Cache, 256 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED
7BH Code and Data L2 Cache, 512 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED
7ch Code and Data L2 Cache, 1024 KB, 8 WAYS, 64 BYTE LINES, DUAL-SECTORED
7EH Code and Data L2 Cache, 256 KB, 8 WAYS, 128 BYTE LINES, SECT. (IA-64)
81H Code and Data L2 Cache, 128 KB, 8 WAYS, 32 BYTE LINES
82H Code and Data L2 Cache, 256 KB, 8 WAYS, 32 BYTE LINES
83H Code and Data L2 Cache, 512 KB, 8 WAYS, 32 BYTE LINES
84H Code and Data L2 Cache, 1024 KB, 8 WAYS, 32 BYTE LINES
85H Code and Data L2 Cache, 2048 KB, 8 WAYS, 32 BYTE LINES
88H Code and Data L3 Cache, 2048 KB, 4 WAYS, 64 BYTE LINES (IA-64)
89H Code and Data L3 Cache, 4096 KB, 4 WAYS, 64 BYTE LINES (IA-64)
8AH Code and Data L3 Cache, 8192 KB, 4 WAYS, 64 BYTE LINES (IA-64)
8DH Code and Data L3 Cache, 3096 KB, 12 WAYS, 128 BYTE LINES (IA-64)
90H Code TLB, 4K ... 256M Pages, Fully, 64 Entries (IA-64)
96H Data L1 TLB, 4K ... 256M Pages, Fully, 32 Entries (IA-64)
9bh Data L2 TLB, 4K ... 256M Pages, Fully, 96 Entries (IA-64)
Value description
70h Cyrix Specific: Code and Data TLB, 4K Pages, 4 Ways, 32 Entries
74H Cyrix Specific: ???
77h Cyrix Specific:???
80H Cyrix Specific: Code and Data L1 Cache, 16 KB, 4 WAYS, 16 BYTE LINES82H CYRIX Specific: ???
84H Cyrix Specific: ???
Value description
Others reserved
For example, there is a P6 EAX = 0302_0101H
EBX = 0000_0000h
ECX = 0000_0000H
EDX = 0604_0A43H This P6 processor contains 4K / m Code / Data TLB, 8 8 KB Code / Data L1 Cache and mix 512 KB Code / Data L2 Cache.
Description
# 1 Pay special attention to the multiprocessor system, should be executed.
EAX = 0000_0003H
Enter EAX = 0000_0003H to get the processor serial number # 1
Output EBX = XXXX_XXXXH processor serial number (just Transmeta Crusoe)
ECX = XXXX_XXXXH processor serial number
EDX = xxxx_xxxxh processor serial number
Description
# 1 When PSN is valid.
EAX = 8000_0000h
Enter EAX = 8000_0000H to get the maximum value of the CPUID instruction and the name string of the manufacturer
Output EAX = XXXX_XXXXH maximum
Name string of EBX-EDX-ECX manufacturers
Authenticamd AMD
Keep Cyrix
Keep Centaur
Intel
Transmetacpu Transmeta
Keep National Semiconductor
Extended EAX = 8000_0001H
Enter EAX = 8000_0001H Get Processor Family / Model / Stepping and Features Flags # 0
Output EAX = 0000_0xxxh processor Family / Model / Stepping
Family family is BITS 11..8.
5 AMD K5
Centaur C2
Transmeta Crusoe TM3X00 and TM5x00
6 AMD K6
VIA Cyrix III
7 AMD K7
Model Model is BITS 7..4.
AMD K5 1 5K86 (Pr120 or PR133)
2 5k86 (PR166)
3 5k86 (PR200)
AMD K6 6 K6 (0.30 μm)
7 k6 (0.25 μm)
8 k6-2
9 K6-III
D K6-2 or K6-III (0.18 μm)
AMD K7 1 Athlon (0.25 μm)
2 Athlon (0.18 μm)
3 DURON (sf core)
4 Athlon (TB Core)
6 Athlon (PM Core)
7 DURON (MG Core)
8 Athlon (TH Core)
A athlon (Barton core)
Centaur 8 C2
9 C3
VIA Cyrix III 5 Cyrix M2 Core
6 Winchip C5a Core
7 Winchip C5B Core (if Stepping = 0..7)
7 Winchip C5C Core (if Stepping = 8..f)
8 Winchip C5C-T Core (if Stepping = 0..7)
Transmeta 4 Crusoe TM3X00 and TM5X00
Stepping step is BITS 3..0.
Stepping's value is the details of the processor .EDx = xxxx_xxxxh Feature Flags Description of Indicated Feature
Bit 31 (3DNOW!) 3DNOW!
Bit 30 (3DNOW! ) Extended 3DNOW!
Bit 29 (LM) AA-64, Long Mode (that is, AMD X86-64 instruction set)
Bit 28 Reserved
BITS 27..25 reserved
Bit 24 (MMX )
Bit 24 (FXSR) CYRIX SPECIFIC: Extended MMX
AMD K7: FXSAVE / FXRSTOR, CR4.OSFXSR
Bit 23 (mmx) MMX
Bit 22 (MMX ) AMD Specific: MMX-SSE AND SSE-MEM
Bit 21 retained
Bit 20 (Nx) Efer.nxe, P? E.NX, #PF (1xxxx)
Bit 19 (MP) MP-CAPABLE # 3
Bit 18 Reserved
Bit 17 (PSE36) 4 MB PDE BITS 16..13, Cr4.pse
Bit 16 (FCMOV)
BIT 16 (PAT) FCMOVCC / F (U) COMI (P) (IMPLIES FPU = 1)
AMD K7: PAT MSR, PDE / PTE.PAT
Bit 15 (CMOV) cmovcc
BIT 14 (MCA) MCG _ * / MCN_ * MSRS, CR4.MCE, #MC
Bit 13 (PGE) PDE / PTE.g, Cr4.pge
Bit 12 (mtrr) mtrr * msrs
Bit 11 (SEP) Syscall / Sysret, Efer / Star MSRS # 1
Bit 10 Reserved # 1
Bit 9 (APIC) APIC # 2
Bit 8 (CX8) CMPXCHG8B
Bit 7 (MCE) MCAR / MCTR MSRS, CR4.MCE, #MC
Bit 6 (PAE) 64bit PDPTE / PDE / PTES, CR4.PAE
Bit 5 (MSR) MSRS, RDMSR / WRMSR
Bit 4 (TSC) TSC, RDTSC, CR4.TSD (Doesn't Imply MSR = 1)
Bit 3 (PSE) PDE.ps, PDE / PTE.RES, CR4.PSE, #PF (1xxxb)
Bit 2 (de) cr4.de, dr7.rw = 10b, #ud on mov from / to DR4 / 5
Bit 1 (VME) CR4.VME / PVI, EFLAGS.VIP/VIF, TSS32.IRB
Bit 0 (FPU) FPU
Description content
# 0 Intel processor does not support; return value EAX, EBX, ECX, and EDX are 0.
# 1 AMD K6 processor, Model 6, Uses uses the tenth directive SEP.
# 2 If the APIC is invalid, the APIC is read 0.
# 3 AMD CPUID = 0662H K7 processor If it is a version with multiprocessor capabilities, 0
EAX = 8000_0002H, 8000_0003H, and 8000_0004H
Enter EAX = 8000_0002H to get the first part of the processor name
EAX = 8000_0003H Get the second part of the processor name
EAX = 8000_0004h gets the third part of the processor name
Output EAX
EBX
ECX
EDX processor name string # 1
AMD K5 AMD-K5 (TM) processor
AMD K6 AMD-K6TM W / MultiMedia Extensions
AMD K6-2 AMD-K6 (TM) 3D processor
AMD-K6 (TM) -2 processor AMD K6-III AMD-K6 (TM) 3D processor
AMD-K6 (TM) -III processor
AMD K6-2 AMD-K6 (TM) -III processor (?)
AMD K6-III AMD-K6 (TM) -III processor (?)
AMD K7 AMD-K7 (TM) processor (MODEL 1)
AMD Athlon (TM) processor (Model 2)
AMD Athlon (TM) processor (Models 3/4, 6/7, And 8 - Programmable)
Centaur C2 # 2 IDT Winchip 2
IDT Winchip 2-3D
VIA Cyrix III Cyrix III (TM) (?)
Via Samuel (?)
VIA EZRA (?)
Intel P4 Intel (R) Pentium (R) 4 CPU XXXXMHZ (Right-Justified, Leading Whitespaces) By the way, Intel is only supported by P4.
Transmeta Transmeta (TM) Crusoe (TM) processor TMXXXX
Description content
# 1 is an array of characters, ending at 0h.
# 2 Winchip Support Decision to support 3D Now! .
EAX = 8000_0005H
Enter EAX = 8000_0005H to get the L1 cache capacity and the number of portions # 1
Output EAX 4/2 MB L1 entry information
Eax's bit description
31..24 Data TLB Associative (FFH = FULL)
23..16 Data TLB Entries
15..8 code TLB Associative (FFH = FULL)
7..0 Code TLB Entries
EBX 4 KB L1 entrance information
BITS DESCRIPTION
31..24 Data TLB Associative (FFH = FULL)
23..16 Data TLB Entries
15..8 code TLB Associative (FFH = FULL)
7..0 Code TLB Entries
ECX DATA L1 Information Description
BITS DESCRIPTION
31..24 Data L1 Cache Size In KBS
23..16 Data L1 Cache Associative (FFH = FULL)
15..8 Data L1 Cache Lines Per Tag
7..0 Data L1 Cache Line Size in Bytes
EDX Code L1 Information Description
BITS DESCRIPTION
31..24 Code L1 Cache Size In KBS
23..16 Code L1 Cache Associative (FFH = FULL)
15..8 Code L1 Cache Lines Per tag
7..0 Code L1 Cache Line Size in Bytes
Description Description
# 1 CYRIX processor use 0000_0002h to do a similar description
EAX = 8000_0006h
Enter EAX = 8000_0006H to get the number of cache capacity and portions of the L1
Output EAX 4/2 MB L2 entry information # 1
Bit description
31..28 Data TLB Associative # 2
27..16 Data TLB Entries
15..12 Code TLB Associative # 2
11..0 Code TLB Entries
EBX 4 KB L2 entry information
Bit description
31..28 Data TLB Associative # 127..16 Data TLB Entries
15..12 Code TLB Associative # 1
11..0 Code TLB Entries
ECX unified L2 cache information # 32
BITS DESCRIPTION
31..16 # 4 unified l2 cache size in kbs # 3
15..12 # 4 unified L2 Cache Associative # 1
11..8 # 4 unified l2 cache lines per tag
7..0 Unified L2 Cache Line Size in Bytes
Description description
# 1 0000B = L2 OFF, 0001B = Direct mapped, 0010B = 2-Way, 0100B = 4-Way, 0110b = 8-Way, 1000B = 16-WAY, 1111B = FULL
# 2 AMD K7 processor L2 Cache must depend on this information.
# 3 AMD PUID = 0630H K7 processor (DURON) has 64 kB level 2 cache, but the report is only 1KB.
# 4 VIA CYRIX III CPUID = 0670..068FH (C5B / C5C) processor error report BITS 31..24, 23..16, and 15..8.
EAX 8000_0007H
Input EAX = 8000_0007H Power Management Information (EPM)
Output EDX EPM FLAGS
Bit description
31..3 reserved
2 (VID) VOLTAGE ID Control Supported
1 (FID) FREQUENCY ID Control Supported
0 Temperature Sensing Diode Supported
EAX = 8000_0008H
Enter EAX = 8000_0008H to get address size information
Output EAX address size information
Bit description
31..16 reserved
15..8 Virtual Address Bits
7..0 Physical Address Bits
Transmeta EAX = 8086_0000h
Enter EAX = 8086_0000H to get the maximum support and vendor string of CPUID
Output EAX = XXXX_XXXXH maximum support EAX = L
EBX-EDX-ECX vendor string
Transmetacpu Transmeta Processor
Transmeta EAX = 8086_0001H
Enter EAX = 8086_0001H to get processor information
Output EAX = 0000_0xxxh processor information
Family the family is encoded in bits 11..8.
5 Transmeta Crusoe TM3X00 and TM5x00
Model the model is encoded in bits 7..4.
Transmeta 4 Crusoe TM3X00 and TM5X00
Stepping the stepping is encoded in bits 3..0.
The Stepping Values Are Processor-Specific.
EBX = aabb_ccddh hardware revision (A.B-C.D), IF 2000_0000h: See Eax = L 8086_0002h Register Eax Instead
ECX = XXXX_XXXXH NOMINAL CORE CLOCK FREQUENCY (MHz)
EDX = xxxx_xxxxh feature flags description of indeicated featurebits 31..4 reserved
Bit 3 (LRTI) Longrun Table Interface
Bit 2 (???) unknown
Bit 1 (lr) longrun
Bit 0 (BAD) Recovery CMS Active (Due to a failed upgrade)
Transmeta EAX = 8086_0002H
Enter EAX = 8086_0002H to get processor information
Output EAX XXXX_XXXXH Reserved or Hardware Revision (XXXXXXXH)
See Eax = L 8086_0001h Register Ebx for Details
EBX AABB_CCDDH Software Revision, Part 1/2 (a.b.c-d-x)
ECX XXXX_XXXXH Software Revision, Part 2/2 (a.b.c-d-x)
Transmeta EAX = 8086_0003H, 8086_0004H, 8086_0005H, And 8086_0006H
Enter EAX = 8086_0003H to get the first part of the information string
EAX = 8086_0004h gets the first part of the information string
EAX = 8086_0005H gets the first part of the information string
EAX = 8086_0006h gets the information string first part
Output EAX-EBX-ECX-EDX Information String # 1
Transmeta 20000805 23:30 Official Release 4.1.4 # 2 (example)
Description
# 1 string ending with 00h.
Transmeta EAX = 8086_0007h
Enter EAX = 8086_0007H to get processor information
Output EAX XXXX_XXXX Curo Current Clock Frequency (MHz)
EBX XXXX_XXXXH Current Voltage (MV)
ECX XXXX_XXXX current usage (0..100%)
EDX XXXX_XXXX Current Delay (FS)
Mysterious function EAX = 8FFF_FFFEH
Input EAX = 8fff_fffeh unknown # 1
Output EAX 0049_4544H DEI (According to One Source: Divide et impera = DIVIDE AND RULE)
EBX 0000_0000h reserved
ECX 0000_0000h reserved
EDX 0000_0000h reserved
Description
# 1 This method is only supported by AMD K6.
Mysterious function EAX = 8FFF_FFFH
Enter EAX = 8fff_ffffh unknown # 1
Output EAX
EBX
ECX
Edx String NexGenerationAmd
Description
# 1 This method is only supported by HE AMD K6.
other
Input eax = xxxx_xxxx Other
Output eax = xxxx_xxxxh
Ebx = xxxx_xxxxh
ECX = xxxx_xxxxh
EDX = xxxx_xxxx is not clear
code show as below:
Type
TCPUIDRESULT = Packed Record
Eax: DWORD;
EBX: DWORD;
ECX: DWORD;
EDX: DWORD;
END;
TCPUINFO = Packed Record
Name: String [48];
BRAND: WORD;
APIC: DWORD;
Vendor: String [12]; FREQUENCY: REAL
Family: integer;
Model: integer;
Stepping: integer;
Efamily: integer;
Emodel: Integer;
Estepping: integer;
Mmx: boolean;
MMXPlus: boolean;
AMD3DNOW: BOOLEAN;
AMD3DNOWPLUS: BOOLEAN;
SSE: Boolean;
SSE2: bolean;
IA64: Boolean;
X86_64: bolean;
END;
Function CPUID (EAX: DWORD): TCPUIDRESULT;
VAR
Reax, Rebx, Recx, REDX: DWORD;
Begin
ASM
Push EAX
Push EBX
Push ECX
Push Edx
Mov Eax, EAX
// ******************************************************** ******
// CPUID instruction, because Delphi's assembly compiler does not have built-in instructions,
// So use the instrument language code of this command $ 0f, $ A2 to implement
// ******************************************************** ******
DB $ 0F, $ A2
Mov Reax, EAX
MOV Rebx, EBX
Mov Recx, ECX
MOV Redx, EDX
POP EDX
POP ECX
POP EBX
POP EAX
END;
Result.eax: = reax;
Result.ebx: = Rebx;
Result.ecx: = RECX;
Result.edx: = REDX;
END;
Function getcpuspeed: Real;
Const
Timeperiod = 1000;
VAR
Highfreq, Testfreq, Count1, Count2: INT64;
TimeStart: Integer;
TimeStop: integer;
ElapsedTime: DWORD;
StartTicks: DWORD;
EndTicks: DWORD;
TotalTicks: DWORD;
Begin
StartTicks: = 0;
Endticks: = 0;
IF QueryperFormanceFrequency (Highfreq) THEN
Begin
Testfreq: = Highfreq Div 100;
QueryperFormanceCounter (count1);
Repeat
QueryperFormanceCounter (count2);
Until count1 <> count2;
ASM
Push EBX
XOR EAX, EAX
XOR EBX, EBX
XOR ECX, ECX
XOR EDX, EDX
DB $ 0F, $ A2 /// CPUID
DB $ 0F, $ 31 /// RDTSC
Mov StartTicks, EAX
POP EBX
END;
Repeat
QueryperFormanceCounter (count1);
Until count1 - count2> = Testfreq;
ASM
Push EBX
XOR EAX, EAX
XOR EBX, EBX
XOR ECX, ECX
XOR EDX, EDX
DB $ 0F, $ A2 /// CPUID
DB $ 0F, $ 31 /// RDTSCMOV ENDTICKS, EAX
POP EBX
END;
ElapsedTime: = Muldiv (count1 - count2, 1000000, highfreq);
end
Else
Begin
TimeBeginperiod (1);
TimeStart: = TimegetTime;
Repeat
TimeStop: = TimegetTime;
Until TimeStop <> TimeStart;
ASM
Push EBX
XOR EAX, EAX
XOR EBX, EBX
XOR ECX, ECX
XOR EDX, EDX
DB $ 0F, $ A2 /// CPUID
DB $ 0F, $ 31 /// RDTSC
Mov StartTicks, EAX
POP EBX
END;
Repeat
TimeStart: = TimegetTime;
Until TimeStart - TimeStop> = TimePeriod;
ASM
Push EBX
XOR EAX, EAX
XOR EBX, EBX
XOR ECX, ECX
XOR EDX, EDX
DB $ 0F, $ A2 /// CPUID
DB $ 0F, $ 31 /// RDTSC
Mov endticks, EAX
POP EBX
END;
TimeEndPeriod (1);
ELAPSEDTIME: = (TimeStart - TimeStop) * 1000;
END;
Totalticks: = endticks - startticks;
Result: = TotalTicks / ElapsedTime
END;
Function getcpuinfo: tcpuinfo;
Type
Tregchar = array [0..3] of char;
VAR
LVCPUID: TCPUIDRESULT;
I: integer;
Begin
LVCPUID: = CPUID (0);
Result.vendor: = TregChar (LVCPUID.EBX) Tregchar (LVCPUID.EDX)
Tregchar (LVCPUID.ecx);
LVCPUID: = CPUID (1);
Result.frequency: = getcpuspeed;
Result.Family: = (LVCPUID.EAX AND $ F00) SHR 8;
Result.model: = (LVCPUID.EAX AND $ 78) SHR 4;
Result.Stepping: = (LVCPUID.EAX AND $ F);
Result.efamily: = (LVCPUID.EAX AND $ 7800000) SHR 20;
Result.emodel: = (LVCPUID.EAX AND $ 78000) SHR 16;
Result.estepping: = (LVCPUID.EAX AND $ F);
Result.apic: = (lvcpuid.ebx and $ 1FE00000) SHR 23;
Result.brand: = lvcpuid.ebx and $ 7F;
Result.mmx: = (LVCPUID.EDX and $ 800000) = $ 800000;
Result.SSE: = (LVCPUID.EDX and $ 2000000) = $ 2000000;
Result.SSE2: = (LVCPUID.EDX and $ 4000000) = $ 4000000; Result.ia64: = (Lvcpuid.edx and $ 400000) = $ 40000000;
LVCPUID: = CPUID ($ 80000001);
Result.mmxPlus: = (LVCPUID.EDX and $ 800000) = $ 800000;
Result.amd3dNow: = (LVCPUID.EDX and $ 10000000) = $ 10000000;
Result.amd3dNowPlus: = (LVCPUID.EDX and $ 8000000) = $ 8000000;
Result.x86_64: = (LVCPUID.EDX and $ 400000) = $ 40000000;
if (Result.vendor = 'GenuineIntel') and (Result.Family <> 15) OR
(Result.efamily <> 0)).
Result.name: = Result.vendor 'Processor'
Else
Begin
Result.name: = '';
For i: = 2 to 4 do
Begin
Lvcpuid: = CPUID ($ 80000000 i);
Result.name: = Result.name
Tregchar (LVCPUID.EAX)
Tregchar (LVCPUID.EBX)
Tregchar (LVCPUID.ECX)
Tregchar (lvcpuid.edx);
END;
Result.name: = trim (result.name);
END;
END;
Procedure TFORM1.FORMSHOW (Sender: TOBJECT);
Procedure Writesupport (Edit: Tedit; Sup: Boolean);
Begin
IF sup
Edit.text: = 'Support'
Else
Edit.Text: = 'does not support';
END;
VAR
CPU: TCPUInfo;
Begin
CPU: = Getcpuinfo;
EditcPuname.text: = cpu.name;
Editvendor.Text: = cpu.vendor;
Editf.text: = INTTOSTR (CPU.FAMIL);
Editm.Text: = INTTOSTR (CPU.Model);
Editstep.Text: = INTTOSTR (CPU.STEpping);
Editfe.Text: = INTTOSTR (CPU.efamily);
Editme.Text: = INTTOSTR (CPU.EMODEL);
Editstepe.text: = INTSTR (CPU.ESTEpping);
Edit33.Text: = INTTOSTR (CPU.APIC);
Editbrand.Text: = INTTOSTR (CPU.BRAN);
Editspeed.Text: = formatfloat ('###. ##', cpu.frequency);
Writesupport (Editmmx, CPU.mmx);
Writesupport (Editsse, CPU.SSE);
Writesupport (editsse2, cpu.sse2); Writesupport (Editia64, CPU.ia64);
Writesupport (EditmmxP, CPU.mmxPlus);
Writesupport (Edit3DNow, CPU.AMD3DNOW);
Writesupport (Edit3DNowP, CPU.AMD3DNOWPLUS);
Writesupport (editX86_64, cpu.x86_64);
END;
A true CPU detection software is also able to detect cache information, and the like. You can refer to the parameters shown in the table below, and extend in these code.
The information of the CPU is so hard to find. Intel and AMD are still better, and other companies are simply a large sea. I tried my best, I can only sort out.
