Microcomputer bus and interface standard
Since the 1970 US DEC uses the UNIBUS bus on its PDP11 / 20 small computers, with the rapid development of computer technology, various standards, non-standard buss have been introduced. The reason why bus technology can develop rapidly is due to the use of bus structures in system design, production, use, and maintenance. Summary of the following:
· Easy to use module structure design methods to simplify system design;
· Standard bus can get extensive support from multiple manufacturers, easy to produce hardware board and software;
· The module structure is convenient for the expansion and upgrade of the system;
· Easy to troubleshoot and repair, and also reduced costs.
The PC has adopted a bus structure from its birth. Advanced bus technology has a very important impact on the performance of the system bottleneck to improve the performance of the entire microcomputer system, so the bus structure has also continuously evolved during more than 20 years of development. The current bus structure has become one of the important indicators of microcomputer performance.
In addition to the bus technology in the microcomputer system, standard interface technology is also adopted, and its purpose is to facilitate the module structure design, which can be widely supported by multiple vendors, which is easy to produce and compatible external equipment and software. The interface generally refers to an adapter circuit between the motherboard and a certain type of peripherals, which is to solve the matching problem between voltage level, signal form, and speed between the main board and peripherals. Therefore, different types of peripherals require different interfaces, and different interfaces are not universal. For example, the interface between the hard disk and the floppy drive is incompatible, so the floppy drive cannot be accessed on the hard disk interface. On the other hand, due to the current new interface standards, such as USB, IEEE1394, etc., it is allowed to connect to a variety of peripherals, and they are also referred to as peripheral bus. In addition, the new interface AGP for the display system is also known as the AGP bus due to habits (inserted into ISA or PCI bus slots), but in fact it should be an interface standard.
Classification of bus
First let's discuss the classification of the bus. The bus is a collection of various signal lines, which is a public path for transmitting data, address, and control information between components of the computer. In the microcomputer system, there are a variety of buss. These buss can be classified from different levels and perspectives.
1. According to the location of the CPU or other chip, it can be divided into:
· Online bus
· Photograph
In the CPU, the bus used between the register and the arithmetic logic component ALU and the control unit is called the inner bus (i.e., the bus inside the chip); the general bus (BUS) fingerboard, is the CPU Communication with memory RAM, ROM, and input / output device interface. Some materials also also call the inner bus or internal bus (INTERNAL BUS), which is called an external bus or an external bus (External Bus).
The CPU implements the program to take instructions through the bus, and the data exchange of memory / peripherals, in the case of the CPU and peripherals, the bus speed is the maximum factor in the overall performance of the computer.
2. The function of the bus can be divided into:
· Address Bus
·Data Bus
· Control Bus
The generally said bus includes the above three components, the address bus (ABUS) is used to transmit address information, and the data bus (DBUS) is used to transmit data information, and the control bus (CBUS) is used to transmit various control signals. For example, the ISA bus has a total of 98 lines (i.e., 98 pins are ISA slots); there are 16 data lines (constituent data bus), address line 24 (constitutes address bus), and the remaining various strips are control signal lines (constitutes Control bus), ground wire and power cord.
3. The hierarchy of the bus can be divided into:
· CPU bus: including address line (CAB), data cable (CDB), and control cable (CCD), which is used to connect CPUs and control chips. • Storage bus: Includes address line (MAB), data cable (MDB), and control line (MCD) for connecting storage controllers and DRAMs.
• System bus: also known as I / O channel bus, including address line (SAB), data cable (SDB), and control line (SCB) for connecting each expansion plate card on the expansion slot. The system bus has a variety of standards for a variety of systems.
· External bus: used to connect peripheral control chips, such as I / O controllers and keyboard controllers on the motherboard. Includes address line (XAB), data cable (XDB), and control lines (XCB).
CPU bus, storage bus, external bus on system board, different systems use different chip sets. These buss do not exactly, and there is no interchangeability. The system bus is connected to the I / O expansion slot, which can be inserted into a variety of expansion boards in the I / O slot, and are connected to the peripheral adapter as various peripherals. The system bus must have a unified standard to design all kinds of adapter cards in accordance with these standards. Therefore, the bus we actually discussed is the system bus, and various bus standards are mainly the standards of the system bus.
4. The position according to the bus in the microcomputer system can be divided into:
· Internal bus: all kinds of various types introduced above are in the machine bus.
Peripheral Bus - Peripheral Bus: Refers to the bus interface with an external device, is actually an interface standard for peripherals. At present, the popular interface standards in the PC are: IDE, SCSI, USB and IEEE1394. The first two mainly with the hard drive, optical drive, etc. The two new external bus can be used to connect a variety of external devices.
5. System Bus
The bus we have to discuss is mainly the system bus. The system bus on the PC can be divided into various standards such as ISA, EISA, MCA, VESA, PCI, AGP.
· ISA (INDUSTRY Standard Architecture) is a bus industry standard for IBM's 286 / AT computers. Also known as the AT standard.
· MCA (Micro Channel Architecture), is a microchannel bus structure developed by IBM for its PS / 2 system. Since the execution is the license system, it is not possible to obtain effective promotion.
· EISA (Extended Industry Standard Architecture), is a bus extended industry standard for the 32-bit CPU designed by EISA Group (1988 composed of COMPAQ, HP, AST, NEC, OLIVETTI, ZENITH, TANDY, etc.).
· VESA (Video Electronics Standards Association), is VESA organization (initiated by IBM, Compaq, etc. in 1992, more than 120 companies participating in) an open bus for designing the Local Bus standard.
• PCI (Peripheral Component Interconnect), is the bus structure launched by the SIG (Special Interest Group). Since 1992, there are famous manufacturers such as Intel, HP, IBM, Apple, Dec, Compaq, NEC, and other famous manufacturers.
AGP (Accelerated Graphics Port) speeds graphics port. It is a bus specification designed to improve video bandwidth. Because it is a point-to-point connection, that is, the connection control chip and the AGP display card, so strictly, AGP is also an interface standard.
6. Local bus
After the graphical user interface (GUI) represented by Windows enters the PC, high-speed graphic drawing capabilities and I / O processing power are required. This not only requires graphical adapter card to improve its performance, but also challenge the speed of the bus. In fact, the speed of peripherals has improved, such as the data transfer rate between the hard disk and the controller has reached 10MB / s, and the data transfer between the graphics controller and the display has reached 69MB / s. It is generally considered that the speed of the I / O bus should be 3 to 5 times the peripheral speed. Therefore, the original ISA, EISA is far from adapting to the requirements, and has become the main bottleneck of the entire system. The local bus is a major development of the PC architecture. It breaks the bottleneck of data I / O, enabling high performance CPUs to make full play. From the structure, the so-called partial bus is a primary bus or management of the ISA bus and the CPU bus. This allows some high-speed peripherals such as graphics cards, hard disk controllers, etc., from the ISA bus to the CPU bus, and match the high-speed CPU bus.
The local bus can be divided into three:
· Special local bus
· VL bus (VESA LOCAL BUS).
• PCI bus (Peripheral Component Interconnect).
The dedicated partial bus is some big companies, such as NEC, Dell, HP, etc., special bus developed for their system, for graphics processing, network transmission, etc. They are non-standard and cannot be universal, nor are they adopted by the majority of compatible machines. The VL bus and PCI bus are general bus, but the VL bus is only a transition standard for 486, which is currently eliminated. 586 microcomputers in the upper grade generally use PCI bus.
Main parameters of the bus
1. Bandwidth of the bus
The band widespoint of the bus is the amount of data that can be transmitted on the bus for a certain period of time, ie the maximum steady state data transfer rate of how much MB is transmitted per second. Two concepts related to bus bandwidth is closely related to the bus level and bus operating clock frequency.
2. The bit wide of the bus
The bit wide refers to the bus of the bus can be transmitted at the same time, namely the concept of 32-bit, 64-bit bus width. The wider the bits wide, the larger the data transfer rate per second, that is, the wider bus bandwidth.
3. Work clock frequency of the bus
The work clock frequency of the bus is in units of MHz, the higher the operating frequency, the faster the bus operating speed, that is, the wider bus band width.
The relationship between the bus bandwidth, the total line is wide, and the bus work clock frequency is easy to understand. The traffic on the highway depends on the number of road lanes and the speed of the vehicle. The more the lane, the faster the vehicle speed, the larger the traffic flow; the bus bandwidth is like the traffic flow of the highway, the bus is wide as the lane on the highway Number, the bus clock operating frequency is equivalent to the vehicle speed, the wider the total line is wider, the higher the bus operating clock frequency, the greater the bus bandwidth.
Of course, the bit width or working clock frequency of unilaterally increasing the bus can only partially improve the bandwidth of the bus, and it is easy to achieve the respective limits. Only the two can make the bid of the bus to a greater increase.
ISA bus
I. Overview
The earliest PC bus is an 8-bit machine-based PC / XT bus that IBM is launched in 1981, called a PC bus. In 1984 IBM introduced 16-bit PC PC / AT, and its bus called AT bus. However, IBM has not published their AT bus specification. In order to improve the external interface card, the ISA bus with IBM / AT original machine bus, namely 8/16 "Industry Standard is jointly developed by Intel Company, IEEE and EISA Group. Architecture) Bus.
Second, the main features and performance indicators of the ISA bus
8-bit ISA extended I / O slot consists of 62 pins, used for 8-bit cards; 8/16-bit expansion slots except for a 8-bit 62-line connector, there is an additional 36 Line connector, this extended I / O slot can support 8-bit card, or support 16-bit card. The main performance indicators of the ISA bus are as follows:
· I / O address space 0100H-03FFH
· 24-bit address line can directly address memory capacity is 16MB · 8/16-bit data cable
· 62 36 pin
· Maximum width 16 (bit)
· The highest clock frequency 8MHz
· Maximum steady-state transmission rate 16MB / s
· Interrupt function
· DMA channel function
· Open bus structure allows multiple CPU sharing system resources
The ISA slot is shown in Figure 2.
The 62-line slot of the A1-A31 and B1-B31 is an 8-bit card slot, which is fully compatible with the PC / XT 8-bit bus. C1-C18 and D1-D18 are 36-wire slots that are increased at the AT bus, and it is used with a 62-wire slot for use with a 16-bit card.
Eisa bus
I. Overview
The ISA bus is convenient for 286 and 386SX, but the 32-bit address and data width of 32-bit address and data width is not enough for the 32-bit address and data width of 386dx, and the 32-bit microprocessor is affected due to insufficient width of its data bus and address bus. Performance is played. For this purpose, the IBM has introduced the MCA microchannel bus technology adopted by the microcomputer, but since IBM uses a strict license system for MCA technology, other manufacturers cannot be used, while MCA is not compatible with PC / XT / AT bus, so In addition to the use of PS / 2 computers, it is not promoted in other compatible machines. In order to compete with MCA bus technology, nine companies such as Compaq, HP, AST, EPSON, NEC, OLIVETTI, TANDY, WYSE, ZEITH DATA SYSTEM (ZDS) were jointly launched in 1988 in 1988, 32-bit microcomputer design "Extended Industry Standard Architecture, the EISA bus.
EISA has good compatibility with ISA, protects the manufacturer and user huge hardware and software investment; while fully utilizing the function of 32-bit microprocessors, making it in graphics technology, optical memory, distribution, network , Data processing and the like are required to function at high speed processing capabilities. The launch of EISA broke the monopoly of IBM MCA structure on microcomputer development.
Second, the main features of EISA
The EISA slot is compatible with the ISA card and is compatible with the EISA card. 32-bit data lines can be used to reach 33MB / s transmission rates when inserting the EISA card. The main performance indicators of EISA have the following advantages compared to ISA:
· Open structure. EISA and ISA are compatible, existing ISA expansion boards can be used on EISA bus
· 32-bit address domain direct addressing range is 4GB
· 32-bit data cable
· Maximum clock frequency 8.3MHz
· Maximum transmission rate 33MB / s
The EISA slot is compatible with the ISA and EISA cards, so in structure and past slots are different, the gold fingers of the EISA card are also double-layer structures. The connection diagram of the EISA slot structure and ISA, EISA is shown in Figure 3.
As shown, the EISA slot appearance is high as the ISA slot or the like, and the double-layer pin structure is used inside, and the two-layer pin is limited by the positioning key. The upper pin pin corresponds to the "Golden Finger" on the ISA card, the pin is A1-A31, B1-B31, C1-C18, and D1-D18. The ISA card will not touch with the lower pin pin due to the limit of the positioning key. The lower pin is designed for the EISA card, corresponding to "Golden Finger" on the EISA card. The pin is E1-E31, F1-F31, G1-G9, and H1-H19. When the EISA board is inserted, the standard notch on the card will avoid the positioning button, and can insert the bottom of the slot, so that "Golden Finger" on the EISA card is each with the slot A, B, C, D, E, F, G , H group pin connections, Figure 3 shows the case where the ISA slot is inserted into the ISA card and the EISA card.
PCI bus
I. Overview
In the 1990s, with the wide application of graphics processing technology and multimedia technology, after the graphical user interface (GUI) represented by Windows, high-speed graphic drawing capabilities and I / O processing capabilities are required. This not only requires graphical adapter card to improve its performance, but also challenge the speed of the bus. In fact, the speed of peripherals has improved, such as the data transfer rate between the hard disk and the controller has reached 10MB / s, and the data transfer between the graphics controller and the display has reached 69MB / s. It is generally considered that the speed of the I / O bus should be 3-5 times the peripheral speed. Therefore, the original ISA, EISA is far from adapting to the requirements, and has become the main bottleneck of the entire system. Therefore, a higher performance requirement is proposed, thereby prompted the bus technology to further develop. In the second half of 1991, Intel first proposed the concept of PCI, combined with more than 100 companies such as IBM, Compaq, AST, HP, and DEC, and the English is full name: Peripheral Component Interconnect Special Interest Group (peripheral components Connect a professional group), referred to as PCISIG. PCI is an advanced local bus that has become a new standard for local bus. The PCI bus slot is shown in Figure 4.
Second, the main performance and characteristics of PCI local bus
The PCI bus is a partial bus that is not attached to a specific processor. From the structure, the PCI is a primary bus inserted between the CPU and the original system bus, which is specifically implemented by a bridging circuit to manage this layer, and implements the interface between the up and down to coordinate the transfer of data. The manager provides signal buffering to support 10 peripherals and maintain high performance at high clock frequencies. The PCI bus also supports bus master control, allowing smart devices to get bus control when needed to accelerate data transfer.
1. The main performance of the PCI bus
· Support 10 sets
· Bus clock frequency 33.3MHz / 66MHz
· Maximum data transmission rate 133MB / s
· Clock synchronization method
· Nothing with the CPU and clock frequency
· Bus width 32 bits (5V) / 64 bits (3.3V)
· Can automatically recognize peripherals
· Special fitness work with Intel's CPU
2. Other features
· Ability to operate in parallel with processor and memory subsystem
· Have an implicit central arbitration system
· Use multiple multiplexing methods (address lines and data cables) to reduce the number of pins
· Support 64-bit addressing
· Complete Multi-Bus Master Ability
· Provide parity checks from address and data
· Convert 5V and 3.3V signaling environment
Third, PCI bus signal definition
49 target devices to pin main control equipment 47
Optional Pins 51 (mainly used for 64-bit extensions, interrupt requests, cache support, etc.)
120 total pins (including power, ground, reserved pins, etc.)
Fourth, PCI bus structure connection method
The basic connection of the PCI bus is shown in Figure 5. From the figure, you can see that the CPU bus and the PCI bus are connected by a bridge circuit (habit called a North Bridge chip). In addition to the bridge circuit, in the chip, other control circuits such as Cache controllers and DRAM controllers are included. Mount high-speed devices on the PCI bus, such as graphics controllers, IDE devices, or SCSI devices, network controllers, etc. Between the PCI bus and the ISA / EISA bus are also connected by bridged circuits (habits called Nanqiao chips), traditional slow devices are connected to the ISA / EISA, inheriting the original resources.
In addition, the PCI bus has some other connection, such as dual PCI bus, PCI to PCI mode, multiprocessor server mode, etc. Given that the relationship is no longer detailed.
5. New Development of the PCI bus
The highest version of the current PCI bus is version 2.1, although theoretically reaches 66MHz clock frequency, but for new CPUs, such as Xeon, Katmai, etc.) and high bus frequency motherboards are completely unable to adapt. The new generation of PCI bus specification in Intel is called PCI-X, which is mainly suitable for desktop boards for 133MHz bus clock frequencies. In addition, Intel is also ready to introduce a bus standard called Mini PCI. MINI PCI's original PCI bus is improved on control lines and functions, reduces the dimensions, making it suitable for portable machines. AGP bus
First, why do I use AGP?
AGP (Accelerated Graphics Port) speeds graphics port. It is a bus specification designed to improve video bandwidth. It supported AGP slots can be inserted into the AGP card compliant with this specification. The transmission rate of its video signal can be increased from 132Mb / s of PCI to 266MB / s (× 1 mode) or 532Mb / s (× 2 mode).
Although the PC's graphics can now be more stronger, it is necessary to complete the meticulous large 3D graphic depiction, the performance of the PCI structure is still limited, in order to make PC's 3D application ability can be higher than the graphic workstation, Intel has developed AGP Standard, the main purpose of launching AGP is to significantly increase the graphics of high-end PCs, especially 3D graphics.
Strictly speaking, AGP cannot be called bus because it is a point-to-point connection, that is, the connection control chip and AGP display card. The purpose of using AGP is to bring 3D graphic data over the PCI bus, and send it directly to the display subsystem. This will break through the system bottleneck formed by the PCI bus.
The limitations of the PCI bus in 3D applications are mainly in 3D graphical depiction. Store not only video data in the PCI display card display memory, but also texture data, the distance between the Z-axis, and Alpha transform data, especially the amount of information of texture data is quite large. If you want to draw detailed 3D graphics, you need to have a lot of memory capacity; plus more fast memory, eventually causing high display card. Therefore, the 3D display card manufacturer expects to increase the storage capacity of texture data and reduce the cost of the product. An effective way is to store texture data from the display to the main memory in order to reduce the capacity of the display memory, thereby reducing the cost of the display card. From the entire system, it is better to increase the display memory is not as good as the main memory. The memory space required to store texture data is determined according to the application, that is, when the application ends, the main memory space it occupies is recovered, and the texture data is not always occupying the main memory.
Unfortunately, when the texture data is flush from the display to the main memory, the bottleneck of the data transmission is transferred from the memory bus on the display card to the PCI bus from the memory bus on the display card. For example, when the 3D graphic of 1024 × 768 × 16-bit true color is displayed, the transmission speed of the texture data requires 200 MB / s, but the current PCI bus has only 133Mb / s only 133MB / s, and thus becoming the main bottleneck of the system.
The data transfer speed required when 3D drawing is shown in the table below:
AGP provides a direct channel between the main memory and the display card. The 3D graphic data is passed through the PCI bus and directly feeds to the display subsystem. This can break through the system bottleneck formed by the PCI bus, thereby achieving a descriptive function of high performance 3D graphics with relatively low prices. The system structure of the AGP bus is shown in Figure 6.
Second, the performance characteristics of AGP
The AGP is based on the 66MHz PCI Revision 2.1 specification. Based on this, the following main functions are expanded:
1. Data read and write operation pipeline operation
Pipelining operation is an enhanced protocol provided by AGP only for the main memory. Due to the use of pipeline operation, the data transfer speed has been greatly improved. 2. Data transmission frequency with 133MHz
AGP uses a 66MHz clock for 32-bit data bus and dual clock technology. Double clock technology allows AGP to transmit double data in a clock cycle, that is, transmit data in both sides (ie rising edge and falling edges) of the working pulse waveform, thereby reaching 133 MHz transmission rate, ie 532Mb / s (133m ×) 4b / s) burst data transmission rate.
3. Direct memory execution DIME
The AGP allows 3D texture data to not store a crowded frame buffer (ie graphics controller memory), and store it in system memory so that the frame buffer and bandwidth are used for other functions. This technique that allows the display card direct operating main memory is called DIME (Direct Memory Excute). It should be noted that although the AGP stores the texture data into the main memory, it can also be referred to as a UMA (Unified Memory Architecture, Unified Memory Architecture) technology. But the UMA used in some low-end machines has the following differences:
• The main memory used by AGP technology (called AGP RAM) does not completely replace the display cache of the display card, and the AGP main memory is just an expansion and supplement to the cache.
• The UMA of the low-end machine is running through the PCI interface, and the speed is slow.
4. Separation of address signals and data signals
Using multiple signal separation technology (demultiplexing) and enhances the speed of random memory access by using the sideband addressed SBA (Sideband Address) bus.
5. Parallel operation
Allows the AGP display card to access the AGP memory while the CPU access system RAM, and the display bandwidth is not shared with other devices, thereby further improving system performance.
Third, AGP work mode
The working mode of AGP is shown in the table below.
As can be seen from the table, it is necessary to truly achieve good 3D graphics processing power, and should be used in 2 × or more working modes. In 1 × mode, due to insufficient bandwidth, it is not suitable for the speed of DIME, and 3D graphics processing capabilities are still unsatisfactory. Therefore, when purchasing a motherboard and an AGP display card, pay attention to whether they support the working mode of the AGP 2 ×. Currently, 4 × mode has not been officially launched.
Fourth, PCI and AGP comparison
The following table lists the performance comparisons of PCI and AGP.
In a system using AGP, since the display card is connected to the main memory by the AGP, the chipset is connected to the main memory, and the data transfer speed of the display chip and the main memory is improved, so that the original data displayed in the display memory is now stored. Memory, which improves the main memory of memory bus using efficiency, and also improves the transmission speed of data of the screen and the transmission speed of the z Buffer (Z buffer), but also reduces the load of the PCI bus, which facilitates the full performance of other PCI equipment. . Due to the PC98 specification, the ISA bus has been canceled, and the ISA device will eventually be eliminated, so it is necessary to move the display card that occupies a large amount of bandwidth of the PCI bus to AGP. Of course, AGP cannot replace PCI because we have said that AGP is just a graphic display interface standard, not a system bus. Both AGP slots and AGP cards are similar to the EISA, and therefore, the size of the AGP slot is reduced. Figure 7 is a two-layer gold finger pin of the AGP card.
IEEE 1394 bus
IEEE 1394 is a serial interface standard that allows computers, computer external devices, and various home appliances to be very simple. From the IEEE 1394, it can be connected to a variety of different peripheral features, or a bus, that is, an external device connected to an external device. The prototype of IEEE 1394 is Fire Wire, which is running on the Apple Mac, which is used and re-specified by IEEE. It defines data transfer protocols and connectivity systems, which can be used to achieve higher performance to enhance computers and peripherals such as hard drives, printers, scanners, and consumer electronics such as digital cameras, DVD players, videos. The connection capability of the phone, etc. Since the corresponding external device also has an IEEE1394 interface function to connect to the 1394 bus, until the digital camera launched by Sony in the third quarter of 1995 plus the IEEE 1394 interface, 1394 really causing extensive attention. With a 1394 interface digital camera, you can edit the processing image, sound data, and performance without delay. Digital cameras, DVD players, and general consumer home appliances, such as VCR, HDTV, audio, etc., can also be connected to each other using IEEE 1394 interfaces. Computer external equipment, such as hard drives, optical drives, printers, scanners, etc., can also utilize IEEE 1394 to transfer data. Overseas bus will change the current computer itself has many additional cards, connecting lines, which connects various peripherals and various household appliances. Computers are also a common home appliance.
When the computer is home to the computer, the future computer will be like the current TV, the consumer may only take the remote control to quickly complete the Internet, play games, control audio-visual audio and video equipment, even control the electric lights in the house, phone, etc. Really realize the intelligence of living room.
1. Main performance characteristics of IEEE 1394
1. Use the "cascaded" to connect to each external device
The IEEE 1394 can connect up to 63 devices on a port, with a tree or chrysanthemum chain structure between the devices. The maximum length of the cable is 4.5m in the device (down 26 pages). It can reach 16 floors in the tree structure, from the host to the last end of the total length up to 72m.
2. Can provide power to the connected device
There are six core wires in the connection cable (Cable) of the IEEE 1394. Two lines of two lines are power cords, which can be supplied to the connected devices; the other four lines are packaged into two pairs of twisted pairs to transmit signals. The voltage range of the power supply is 8-40V DC voltage, and the maximum current is 1.5A. Some low-power devices such as digital cameras can achieve power from the bus cable without having to configure a separate power supply system for each device. Since 1394 can provide a power supply to the device, even if the device is powered off or there is no failure, it does not affect the operation of the entire network.
3. Adopt memory-based address encoding with high-speed transmission capabilities
The bus uses a 64-bit address width (16-bit network ID, 6-bit node ID, 48-bit memory address), regarding resources as registers and memory cells, can be read and written according to the transmission rate of CPU-memory, so there is high speed Transmission ability. The data transfer rate of the 1394 bus can be up to 400Mbps, so it can be applied to various high-speed equipment.
4. Using point-to-point structure (Peer to Peer)
Any two devices that support IEEE 1394 can be connected directly, and do not need to be controlled by computer control, such as in the case of shutting down, can also play a DVD player with digital TVs directly to play an optical disc program.
5. Easy to install and easy to use
Allow hot plug-and-play, no need to shut down to dynamically configure external devices, increase or remove the peripherals, IEEE 1394 will automatically adjust the topology, reset the entire peripheral network.
Second, IEEE 1394 working mode
1. IEEE 1394 The standard defines two bus data transmission modes, namely: BackPlane mode and Cable mode. The BackPlane mode supports the transfer rate of 12.5, 25, 50 Mbps; Cable mode supports 100,200,400 Mbps rates. 1G version is currently being developed. At 400 mbps, only 50% bandwidth can support uncompressed high quality digital video information flow. 2.iee 1394 can provide synchronous (Synchronous) and asynchronous data transfer mode. Synchronous transmission is applied to real-time tasks, while asynchronous transmission is transferred to a specific address (ExPlicit Address). This standard protocol is called Isosynchronous. The device using this protocol can obtain the necessary bandwidth from the 1394 connection. The remaining bandwidth can be used for asynchronous data transmission, and the asynchronous data transfer process does not retain the bandwidth required for synchronous transmission. This treatment makes two transmission modes to which audio, video, and computer data can be reliably transmitted on the same transport medium. It has no effect on the computer's internal bus. The current PCI partial bus can take full advantage of 1394.
USB bus
The USB (Universal Serial Bus) is called a universal serial bus, which is a new generation of interface standards jointly launched by COMPAQ, DEC, IBM, Intel, Microsoft, NEC, and NT (Northern Telecom). Like IEEE 1394, it is also an off-peripheral bus. From a performance, USB is not as good as 1394, but because USB has an IEEE 1394 unacceptable price advantage, USB will coexist with IEEE 1394 in a period of time, manage low and high speed peripherals.
First, the main performance characteristics of USB
1. Have hot plug and play function
USB provides hot plug-and-play connection outside the chassis, connecting the outer settings without opening the chassis, nor does it need to turn off the host power. This feature provides a great convenience for users.
2.USB uses "cascading" to connect to each external device
Each USB device is connected to a USB plug to the previous peripheral USB outlet, and itself provides a USB outlet for a USB peripheral connection. Through this similar chrysanthemum chain, a USB controller can be connected to up to 127 peripherals, while the distance between the two peripherals (cable length) can reach 5 meters. USB unified 4-pin round plugs will replace many string / parallel-port (mouse, modem), keyboard, etc. in the back of the chassis. USB can intelligently identify insert or disassembly, expansion card, DIP switch, jumper, IRQ, DMA channel, and I / O address of the USB chain.
3. Suitable for low speed peripheral connections
According to the USB specification, the USB transmission speed can reach 12Mb / s (12 megabits per second), in addition to the keyboard, mouse, modem, etc., can also be with ISDN, telephone system, digital audio, printer / scanner Waiting for a low speed peripheral connection. Although USB is designed to connect a higher speed peripheral for digital cameras, it is too late because USB bus technology is launched. The IEEE 1394 interface bus has been in digital camera, digital photography, and video playback such as high speed, high bandwidth area (100MB / s or more) acquisition.
The USB interface socket is shown in Figure 8.
Second, IEEE 1394 and USB similarities
1. You can provide plug and play and hot-swap function;
2. Adopting the "cascaded" mode, you can connect multiple devices, avoiding the computer backplane can only provide a small number of sockets, only limitations to the minority connection.
Third, the main difference between IEEE 1394 and USB
1. Currently, the transmission speed of the IEEE 1394 specification is 100 ~ 400MB / s, so it connects to high speed devices such as DVD players, digital cameras, hard drives, etc., and USB is limited by 12MB / s transmission speed limits only low-speed keyboard, microphone , Floppy drive, telephone and other devices.
2. In the topology of IEEE 1394, there is no need to connect 63 devices, and these separate subnets can be connected to the Bridge. IEEE 1394 does not force to control these devices with computers, which means that these devices can work independently. In the topology of the USB, multiple connections must be implemented via HUB. Each HUB has seven connectors, up to 127 machines across the USB network, and must have the existence of a computer as a total control. 3. The topology ofiee 1394 is automatically reset when its external device is increased, including a short wait state of the network; the USB is in Hub to determine the increase or decrease of its connection device, so it can reduce the USB network dynamic reset. Status.
USB and IEEE 1394 have many similar places in functional and design ideas, but their transmission rate is different, and the applicable range is also different. From the current situation, the PC97 standard has been included in the USB specification. The new chipset supports USB, and many of the USB peripheral products have emerged, and the use of USB has been promoted. The IEEE 1394 has not yet supported the bus group for the bus standard, and the number of peripheral products that support 1394 is also very small, so IEEE 1394 is still difficult to form a climate in the short term.
IDE interface
As an interface, both hardware and software are both: interface equipment is hardware, and the interface signal specification standard is software. Interface Signal Standards define each signal line, define content including the attributes of the signal (control signal, state signal, or data signal), direction and effective level (high level effective or low levels). It is only possible to connect to the interface standard. Basic hard disk interface standards have four, namely ST506, IDE, ESDI, SCSI. For the user, do not request a detailed understanding of the details of the interface software, as long as the interface standard can be connected to use. ST506 is the earliest interface standard developed by Seagate.
Esdi's original is Enhanced Small Device Interface, an enhanced small device interface, a high-performance hard disk interface developed by companies such as Maxtor, SHUGART, CDC, and Xebec. Both ST506 and ESDI have been eliminated, and the most widely used in the microcomputer is the IDE and SCSI standards.
Ide, IDE interface standard
The original text of IDE is Integrated Device Electronics, ie integrated equipment electronic components. It is developed by Compaq and produced by Western Digital. The IDE is improved based on the ST506, and its maximum feature is to integrate the controller into the drive. Therefore, in the hard disk adapter card, there is no longer a controller. The biggest advantage of this is to eliminate data loss problems between drives and controllers, making data transmission very reliable. This can improve the number of sectors per track to 30 or more, thereby increasing capacity. Since the controller circuit is incorporated into the driver, the signal line drawn from the drive is no longer the interface signal line between the controller and the driver, but the interface signal line connected to the main system after simply processing. It is different from the ST506 interface. The IDE is connected to a 40-wire unitless connection. In the interface of the IDE, except for the signals on the AT bus, it is basically sent to the hard drive. From this, it can be seen that the IDE is actually a system-level interface, while ST506, ESDI belongs to the device level interface. Therefore, it is also known as an ident interface (Attachment: AT embedded interface).
Since the adapter card has become very simple because the controller is integrated into the drive, the adapter card is no longer used in the microcomputer system, and the adapter circuit is integrated into the system motherboard and there is a special IDE connection. The socket. Ide has been widely used in personal microcomputer systems due to various advantages and low cost.
Second, the enhanced IDE (EIDE) interface standard
Enhanced IDE (Enhanced IDE) is the interface standard developed by Western Digital as replacing IDE. In the microcomputer system using the EIDE interface, the EIDE interface is directly integrated on the motherboard, so you don't have to purchase a separate adapter card. Compared to IDE, EIDE has the following features: 1. Support for large-capacity hard drives, maximum capacity up to 8.4GB. The original IDE standard is due to the limit of the number of hard disk heads (maximum 16), the maximum hard disk capacity of no more than 528MB.
2. EIDE standard supports other peripherals other than the hard disk. The old IDE standard only supports hard drives, so it is just a hard disk standard. EIDE supports tape drives and CD-ROM drives that meet ATAPI interfaces (Attachment Packet Interface) standards. Therefore, when we talk about the object of the IDE connection, we can only say the hard drive, and you can speak EIDE equipment when you talk about the object of the EIDE.
3. Connect more peripherals, up to four EIDE devices. Original IDE only provides an IDE socket, you can only hang two hard drives. EIDE provides two interface sockets, called the first IDE (Primary) interface socket, respectively, respectively, respectively, and the second IDE (Secondary) interface outlet. Each socket can be connected to two devices, named primer and from (slave) devices, respectively. So a total of four devices can be connected. The first IDE interface is also called a primary channel, which is usually connected to a high-speed local bus for hooking high-speed primary IDE devices such as hard drives. The second IDE interface is called auxiliary channel, which is generally connected to the ISA bus, can be used to simulate a secondary IDE device such as a CD-ROM or a tape drive. In the BIOS setting, the user is required to set the number of Secondary IDE Device, the working mode of the master from the device.
4. EIDE has a higher data transfer rate. The maximum burst data of the original IDE drive is only 3MB / s. The burst data transmission rate refers to the speed of reading data from the hard disk buffer, which is commonly used for megabytes (Mb / s) or megabits per second (MB / s). EIDE supports hard disk standard organizational SFFC (Small Form Factor CommitE), in 1993, host transmission standards, such as Pio (Programmed Input / Output) Mode 3 and Pio Mode 4, with burst data transfer rates up to 11.1MB / s and 16.6 MB / S; also supports MultiWord Mode 1 DMA and MultiWord Mode 2 DMA, with burst data transfer rates of 13.3Mb / s and 16.6Mb / s. To illustrate different transmission standards, systems and hard disks supporting Pio Mode 3 or MultiWord Mode 1 DMA are typically referred to as FAST ATA, and system and hard disks supporting Pio Mode 4 or MultiWord Mode 2 DMA are called FAST ATA-2.
5. In order to support large-capacity hard drives, EIDE supports three hard drive operating modes: Normal, LBA, and Large mode.
· Normal normal mode
This is the original IDE method. When the hard disk is accessed in this manner, the BIOS and IDE controllers do not conversion to the parameters. The maximum number of cylindricals supported in normal mode is 1024, the maximum number of magnetic heads is 16, the maximum number of sectors is 63, and the number of bytes per sector is 512. Therefore, the maximum hard disk capacity is supported: 512 × 63 × 16 × 1024 = 528MB.
In this mode, even if the actual physical capacity of the hard disk is large, the accessible hard disk space can only be 528MB.
· LBA (Logical Block Addressing) logic block addressing mode
The hard disk space managed by this mode breaks through 528kb bottlenecks and can reach 8.4 GB. In LBA mode, parameters such as the set cylinders, heads, and sectors are not physical parameters of the actual hard disk. When accessing the hard disk, the logical address determined by the cylinder, the head, sector, etc. is converted to the physical address of the actual hard disk by the IDE controller. In LBA mode, the maximum number of magnetic heads can be set is 255, and the remaining parameters are the same as normal mode. This allows access to accessible hard disk capacity to: 512 × 63 × 255 × 1024 = 8.4 GB.
· Large big hard disk mode
This mode can be employed when the cylindrical surface of the hard disk exceeds 1024 and does not support LBA. The method taken by the LARGE mode is to divide the cylindrical number by 2, multiplied the number of the head by 2, the total capacity of the result is unchanged. For example, in the Normal mode, the number of pillars is 1220, the number of heads is 16, and the number of column is 610, the number of heads 32 is 32. In this way, the number of cylindricals is less than 1024 in DOS, which is normal. The opposite conversion process is completed by the BIOS INT 13H to achieve the correct hard disk address. The largest hard disk capacity supported by the LARGE mode is: 512 × 63 × 32 × 512 = 528MB users can select settings in the above three working modes depending on the actual hard disk configured.
Third, Ultra DMA33 and ULTRA DMA66 interface standards
After the ATA-2 standard is launched, the SFFC has launched the ATA-3 standard. The main feature of the ATA-3 standard is to improve the security and reliability of ATA-2. The ATA-3 itself does not define a higher transmission mode. In addition, the ATA standard itself only supports hard drives. We said that EIDE supports tape drives and CD-ROM drives that meet ATAPI interface standards, but these ATAPI devices and hard drives have a lot of differences, so they need to be processed by specialized drivers. To this end, SFFC will introduce the ATA-4 standard, which integrates ATA-3 and ATAPI and supports higher transmission mode. Before the ATA-4 standard is not officially launched, the Ultra ATA (Ultra DMA) standard is launched as a transitional standard, Quantum and Intel.
The first standard of Ultra ATA is Ultra DMA33 (UDMA33), and some people call it ATA-3. Main boards and hard drives that meet the standard have been put on the market in 1997. The main features of UDMA33 are as follows:
1. Through the improved driver, take advantage of the performance of the hard disk controller, so that the hard disk avoids excessive intervention of the CPU during the data transfer, making the system's parallel work capacity further improved.
2. Data transmission can be performed on the upper and lower phases of the timing pulse, and the transmission rate is doubled than the hard disk having a single phase. Therefore, its burst data transmission rate can be increased from 16.6 Mb / s to 33MB / s. However, due to system overhead, the actual bandwidth does not reach 33MB / s. Several major UDMA33 hard drives were measured at 26MB / s ~ 30MB / s.
3. Generate a strobe signal from the hard disk and simultaneously send the data in the buffer to the bus, avoiding the delay caused by the host's sending signal.
Ultra DMA66 (or Ultra ATA-66) is the latest standards made by Quantum and Intel in February 1998. Ultra DMA66 is mainly improved to Ultra DMA33 in the following aspects:
1. Further improve the data transfer rate, its burst data transfer rate can reach 66.6MB / s.
2. A new CRC cycle redundancy check. The host and hard disk simultaneously calculate the CRC when the data is transmitted data, and store it in its own register. After the burst transmission is over, the host sent values in the CRC register to the hard disk and compared to the value in the hard disk CRC register, thereby further improving the reliability of data transmission.
3. Change the 80PIN cable (retaining 40PIN cable compatible with existing computers) to ensure that the interference between adjacent signal lines is reduced in high-speed data transmission.
While Intel has not released a chipset that supports Ultra DMA66 hard disk mode, the VIA Apollo Pro chipset has provided support for Ultra DMA66 hard drives. Some motherboards, such as Pariop P2-112A also provided interfaces that support Ultra DMA66 hard drives. There are currently Ultra ATA-66 hard drives on the market.
Use UDMA33 / 66 standard must have the following conditions:
· Motherboard (control chipset) supports UDMA33 / 66 specification;
· Hard disk supports UDMA33 / 66 specification;
· Correctly install the UDMA33 / 66 driver of the hard drive.
SCSI interface
SCSI's original text is the Small Computer System Interface, a small computer system interface. SCSI is also a system-level interface that can be connected to various external devices with SCSI interface standards such as hard drives, scanners, discs, printers, and tape drives. These peripherals using SCSI standards itself must have the corresponding peripheral controller. SCSI is only used in small machines early, and in recent years, it has been adopted in the PC. SCSI is an interface standard (called SCSI-1) published by the National Standard Association (ANSI) in June 1986. In 1990, SCSI-2 standard was launched. The main features of the SCSI interface standard are as follows: 1. SCSI is a system-level interface that can be connected to various external devices with SCSI interface standards such as hard drives, scanners, discs, printers, tape drives, communication devices, and the like. The total number of host adapters and SCSI peripheral controllers on the bus is 8.
2. SCSI is a multi-task interface with bus arbitration functions. Therefore, the adapters and controllers on the SCSI bus can work in parallel, and multiple peripherals under the same SCSI controller can work in parallel.
3. SCSI can transmit data in synchronous mode and asynchronous mode. SCSI-1 in synchronous mode of data transmission rate is 4Mb / s, which is 1.5Mb / s in an asynchronous mode, up to 32 hard drives. All signals of the SCSI-1 interface are transmitted through a 50-wire flat cable, including 9 data lines and 9 control and state signal lines. It is characterized by simple operation timing and has a bus arbitration function. Subsequently launched SCSI-2 standards increased a 68-wire cable, expand the width of the data signal to 16/32 bits, and its synchronous data transfer rate reached 20Mb / s.
4. SCSI can be divided into single-ended transmission mode and differential transmission. Single-ended SCSI cables cannot exceed 6 meters, and if the data transfer distance exceeds 6 meters, a differential SCSI transmission method should be used.
5. The equipment on the SCSI bus does not have a master from the parties, and both parties are equal. The high-level command is communicated between the startup device and the target device, and does not involve the specific physical characteristics of peripherals. Therefore, it is very convenient and adaptable, which is convenient for system integration.
Since the 1990s, the ANSI SCSI Board began to develop SCSI-3 specification. The SCSI-3 specification is a multi-layer structure that adds three protocols in addition to the original parallel protocol: fiber optic channel protocol, serial protocol, and block transport protocol. Therefore, there are four interfaces: SCSI-3 parallel interface, SCSI-3 fiber channel interface, IEEE 1394, and SCSI-3 serial interface. These new interfaces will appear in the form of a PCI card. IEEE 1394 has been described earlier, which is actually a serial standard based on SCSI-3. The structure of SCSI-3 is shown in Figure 9. The SCSI-3 protocol is undoubtedly a more ideal standard. It is currently in the design process, and it is necessary to fully implement specifications and enter practical possibilities require a longer time.
At the same time, the ANSI SCSI Committee has also introduced its Ultra SCSI regulation as a transitional solution. In theory, the maximum data transfer rate of Ultra SCSI is increased to 40Mb / s. However, Ultra SCSI acts as a parallel bus, does not solve the harsh requirements of SCSI to cable wiring, and its high-speed data transmission rate makes cable length and cable quality more prominent. Under single-end mode, the maximum length of the Ultra SCSI cable cannot exceed 1.5 meters; in a differential mode, although the longer cable can be supported, it must provide a separate ground wire for each data cable, so the cost is high, while There is a problem of installation and compatibility. In order to solve the above problem, the Ultra2 SCSI (LVD) specification is introduced in 1998, and the LVD represents a low voltage difference. The main feature of Ultra2 SCSI (LVD) is: 16-bit data cable; the highest data transfer rate is 80Mb / s; the cable length can be up to 12 meters. There is currently some hard disk market for Ultra2 SCSI (LVD), such as Tuntel's Atlas three generations, IBM's UltraStar et al. In September 1998, the ULTRA160 / M interface standard based on Ultra3 SCSI was further published, further increased the data transfer rate to 160MB / s. Quantum also launched the first hard disk ATLAS10K and ATLAS four generations that support Ultra160 / M interface standards in November 1998. SCSI should be a good choice for the PC. It is not only an interface, but also a bus. I believe that with the further development of technology, SCSI will also be widely used in the microcomputer system and peripherals like EIDE.
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