Synchronous reverse and disturb code:
1. Principle:
In Fig. 1, the initial value of the register of the PN code generator is: 100101010000000. MPEG2 data streams, each 8 data frames form a data set. The register of the PN code generator is initialized at the beginning of the transmission of each data group. In order to provide this initialization signal, the synchronization byte of the first MPEG2 data frame in each set of data is reversed, ie 47h reversible B8H. All synchronization bytes in the MPEG2 data stream do not participate in the disturb code.
When software programming, first use a matrix RADATA to simulate the register of the PN code generator and give the same initial value as the register of the PN code generator. Then determine the input data to identify it is synchronization byte or information bytes. When the input data is information byte, the 14th element Radata (14) of the information bit and the PN code generator register matrix.
And the 15th element Redata (15) is used to perform the scrambling code, where the result is stored in the output matrix Randout. When the input data is the synchronization byte, the sync byte does not participate in the disturb code, and when the synchronization byte is the synchronization byte of the first MPEG2 data frame in each set of data, the synchronization byte is reversed.
Note: 1. The initial value of the register of the PN code generator is set to: 100101010000000
2. The PN code generator is initialized once in transmitting each data set (8 data frames)
3. Synchronization byte of the first MPEG2 data frame in each set of data is inverted
4, MPEG2 data streams all synchronization bytes do not participate in the disturb code
5, the decoding portion and the decoding principle are exactly the same
The following is the source program:
//Initialize variables
// int TEMP1 [8], TEMP2 [8];
Int enable, _redata, enabledata
Int InputData [8], OutputData [8];
INT Redata [15]; // Register
BYTE OUTPUT [8] [204] = {0};
For (int m = 0; m <= 7; m )
{
For (int N = 0; n <= 187; n )
{
// m = 0 and n = 15 indicate the initialization register and the symbol of the synchronization byte
IF (m == 0 && n == 0)
{
// Initialization Register RedtaTA
For (int i = 0; i <= 14; i )
{
IF (i == 0 || i == 3 || i == 5 || i == 7)
{
REDATA [I] = 1;
}
Else
{
REDATA [I] = 0;
}
}
/ / Synchronous byte press Bit
OUTPUT [M] [16 N] = ~ INPUT [M] [16 N];
}
// The rest of the synchronization bytes are not tuned in scrambling, according to the original byte output
Else IF (M! = 0 && n == 0)
{
Output [M] [16 N] = INPUT [M] [16 N];
}
// Information bit (non-synchronization byte) scrambled
Else
{
For (int J = 0; j <= 7; j )
{
// Read the information in the byte input input
InputData [J] = INPUT [M] [16 N]% 2;
// Byte INPUT right shift
INPUT [M] [16 N] >> = 1;
}
// scrambling operation
For (int i = 0; i <= 7; i )
{
_Redata = redata [13] ^ redata [14];
For (int J = 14; J> = 1; J -)
{
Redata [J] = Redata [J-1];
Redata [0] = _ redata;
Enabledata = enable & _redata;
Outputdata [i] = enabledata ^ InputData [i];
}
/ / The bits after the scramble give the byte Output
For (i = 0; i <= 7; i )
{
OUTPUT [M] [16 N] = OUTPUT [M] [16 N] | ((byte) OutputData [i] << 1);
}
}
}
}
