Continued GCC compiler
1. Write makefile
A lot of packages on UNIX systems are automatically compiled using the make programs and makefile files. The purpose of the make program is to automatically determine which parts of a package need to be recompiled, and compile them with a specific way, and use Make. It is great to reduce the time spending the compiler because it can eliminate unnecessary reconstruction.
To use make, you must write a Makefile file, which describes the contact between the various files in the package, provides a command to update each file. In a package, it is usually the executable file updated by the connection target file. The target file is updated by the compilation source file.
When a proper makefile exists, each time we change some source files, use simple shell commands: make
Will be sufficient to complete all the necessary recompilation, the Make program uses the Makefile data and the latest change time to update the latest changes to what files need to be updated; for each file that needs to be updated, the Make program uses the command defined in Makefile to update the commands defined in Makefile. it.
If the Make program does not use the -f option to specify a makefile.make will look for the following files in the current directory: gnumakefile, makefile, makefile. Because his first letter is uppercase, usually listed in the directory The front of the list.
Hereinafter, the rules for writing the Makefile file are written:
Makefile files include some targets for each target, provide the name of other targets or files related to this goal and a set of commands to implement this goal. The so-called target is a task that make programs to complete, target Usually the file name, or it is not; the so-called correlation, the completion of a target depends on some other target or files, and the following will give an example of a simple Makefile file:
# 开 # 注 行 行
# A simple Makefile example
PROG: Prog.o Subprog.o
GCC -0 Prog Prog.o Subprog.o
Prog.O: prog.c prog.h
gcc -c -i -o prog.o prog.c
Subprog.o: Subprog.c
gcc -c -o subprog.o subprog.c
Clean:
Rm -f prop * .0
The above Makefile defines four goals: prog, prog.o, subsprog.o, clean. Target starts from the left side of each row, and then follow one colon (:), if there is any other with this target Targets and files, listed them behind the colon and spaced apart in space. Then, one row starts to write a set of shell commands in this goal.
Under normal circumstances, call the Make command to enter: make Target
Target is one of the goals defined in the makefile file. If Target is omitted, make the first target defined in the Makefile file. For the Makefile example above, the separate make command is equivalent to: make prog
Make generates a new shell for each command it execute. The result is that the command executed by the shell is only valid in a single command line. Especially the CD command, it can only affect his command line, such as the following command:
CD ../lib
GCC -O Subprog.o Subprog.c
For the second line, the CD command in the first line is invalid. To enter the ../lib directory before compiling subprog.c, you can use the following command:
cd ../lib;gcc -o subsprog.o subsprog.c
In Makefile, you can use the continuation number (/) to decompose a separate command to a few rows. But pay attention to any characters without any characters behind the continuation number.
Make is a method that is retrofitable when checking if a goal is out of date and needs to be updated. Make To build all the files relying on the target before building a goal, and recursively advance, ensuring that these files are up to date. Make uses the following steps to generate a goal:
1. If a goal does not exist as a file, he is outdated. Command Make Target always performs this task 2. Make Checks all targets related to the target.
3. Removing from the formation, updating all the outdated goals; only when all the goals depend on the target are already the latest, this goal can be updated
Come look at the process of target updates through the above Makefile file example. Now suppose to modify the file subprog.c, use the following command to update the target PROG: make Prog
Since the target PROG depends on the target Prog.o and Subprog.o. We must check if the target prog.o and subprog.o are outdated. Target Prog.O depends on Prog.c and Prog.h. Check the target file prog.o and source file prog.c and prog.h's date, found that PROG.O is new than the source file he rely on, that is, it is not too time. In checking subprog.o, he relies on Subprog.c. Since we edited the subprog.c file, his date is more than the date of the target file Subprog.o. That is, Subprog.o is over. We update it with the shell command to define the target subprog.o:
gcc -c -o subprog.o subprog.c
Since the target subprog.o is outdated and updated, the target Prog is outdated, to complete the Make PROG task, you must use a set of shell commands to define the PROG to be more.
GCC -O Prog Prog.o Subprog.o
If we first compile the above software, because the target files such as prog, prog.o, subs rog.o do not exist, all target prog, prog.o and subprog.o are outdated, and must be updated. All commands for these goals must be performed on the bottom.
In the above Makefile example, a target Clean.clean target is also a dedicated target in Makefile, that is, deleting all target modules.
Another commonly used target module is install. He usually copies the other files required to compile the executable and program run to the specified installation directory and set the corresponding protection.
To simplify the writing of the command, some macro (Macro) can be defined in the makefile and use several predefined abbreviations.
Here are a few very common abbreviations:
$ @ Represents the full name of this goal
$ * Represents the target name of the suffix has been deleted
$ According to this abbreviation: the front Makefile example can be rewritten: # 开 # 注 行 行 # A simple Makefile example PROG: Prog.o Subprog.o GCC -O $ @ prog.o subsprog.o Prog.O: prog.c prog.h gcc -c -i -o $ @ $ < Subprog.o: Subprog.c GCC-CO $ @ $ *. c Clean: Rm -f prop * .0 A macro definition is written from the left side of a line, with the following format: Macro-name = macro-body When Make processes the makefile, use Macro-Bodt instead of the $ (macro-name) string. Examples of Makefile above can be used to define macros to make it more concise: # 开 # 注 行 行 # A simple Makefile example Depends = prog.o subprog.o PROG: $ (Despends) GCC -O $ @ $ (Depends) Prog.O: prog.c prog.h gcc -c -i -o $ @ $ < Subprog.o: Subprog.c GCC-CO $ @ $ *. cclean: Rm -f prop * .0 When defining a set of compilation options, the macro definition is also useful, the following macro defines two compile options. Cflags = -ddebug -g We can compile the target files used to debug with the following commands in Makefile. GCC -C $ (cflags) -o prog.o subprog.o If there is no command to construct this goal in the Makefile file, the Make program will apply an implicit rule. The Make program predefines some implicit rules, and each implied rule applies to a combination of target types and his related types. The implied rules are implemented by the suffix rules. Target implicit rules with those suffixes are defined by the related target list of the Make program's built-in target. Suffixes. The default is: .. Out, .a, .ln, .o, .c, .cc, .c, .p, .f, .f, .r, .y, .l, .s , .S, .mod, .ssym, .def, .h. The target or related type of the object or related type in all implicit rules must be one of the above categories. If you don't want to use Make's implicit rules, you can define your suffix rules yourself, as shown below: .c.o gcc -c -g -ddebug -dhelp_fifle = / "Help /" -o $ *. o $ Suffix rules apply to all UNIX versions of Make programs, GNU's Make program provides a more convenient rule definition method, called pattern rules. The format of the pattern rule is similar to the general definition in Makefile, but it uses percent sign (%) as a wildcard, as shown below: % .O:%. c GCC $ (CFLAGS) -C $ Indicates the rules of the .o file from the .C file .o. Mode rules do not depend on the suffix list. 2, generate makefile using Automake and AutoConf Refer to this article easily produces Makefile files
