2. Control registers and system address registers
80386 Control Register and System Address Register As shown in the table below. They are used to control work mode, control the implementation of segmentation management mechanisms and paging management mechanisms.
Control register crxbit31bit30-bit12bit11-bit5bit4bit3bit2bit1bit0CR0PG00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Bit47-bit16bit15-bit0 Global Descriptor Table Register GDTR Base Site Boundary Interrupt Descriptor Table Register IDTR Base Squit Space
Bit15-bit0 local descriptor table register LDTR Select Subtrial Status Segment Register Tr Selection Sub
Bit31-Bit0bit31-bit0bit11-bit0 base site boundary attribute
<1> Control Register
As can be seen from the above, 80386 has four 32-bit control registers, named bits CR0, CR1, CR2, and CR3, respectively. However, CR1 is retained for future development of processors, and CR1 cannot be used in 80386, otherwise it will cause an invalid instruction operation. CR0 includes a control bit indicating a processor operating mode, including a control bit that enables and disable the paging management mechanism, contains control bits that control the floating point coprocessor operation. CR2 and CR3 are used by paging management mechanisms. Bits 0- Bits 30 and CR3 in CR0 are in the position of 0 to 11, which cannot be a random value, must be 0.
The control register CR0 is low of 16 bits equivalent to 80286 machine status word MSW.
Protection control position
The bit 0 in the control register CR0 uses PE tags, bit 31 with PG tag, which controls the operation of the segment and paging management mechanism, so it is called the protection control bit. PE control segmentation management mechanism. PE = 0, the processor runs in real mode; PE = 1, the processor runs in the protection mode. PG Controls Paging Management Mechanism. PG = 0, disable the paging management mechanism, at which point the linear address generated by the segmentation management mechanism is used directly as a physical address; pg = 1, enable the paging management mechanism, at which time the linear address is converted by the paging management mechanism. Specific introduction to the paging management mechanism is carried out in later articles.
The following table lists the processor works by using PE and PG bit. Since only the paging mechanism can be enabled in the protection mode, although two bits can be 0 and 1, there are four combinations, but only three combinations are valid. PE = 0 and pg = 1 is an invalid combination, so a value of the PG is 1 and the value of PE is entered into the CR0 register will cause universal protection.
It should be noted that the change of the PG bit will enable the system to enable or disable the paging mechanism, so the PG can only be changed only if the code of the executed program and at least part of the data have the same address in linear address space and physical address space. Bit.
PG and PE bit and processor working mode PGPE processor work mode 00 real mode 01 protection mode, disable paging mechanism 10 illegal combination 11 protection mode, enable paging mechanism
2. Coordinator Control Bit
The bit 1-bits 4 in the control register CR0 are respectively marked as MP (arithmetic presence bits), the EM (analog bit), the TS (task switching), and the ET (extended type bits), which control the operation of the floating point coprocessor.
When the processor is reset, the ET bit is initialized to indicate the type of digital coprocessor in the system. If there is an 80387 coprocessor in the system, the ET position 1; if there is an 80287 coprocessor or there is no coprocessor in the system, the ET bit is clear.
The execution of the EM bit controls floating point instructions is to use software simulation or executed by hardware. When EM = 0, the hardware control floating point command is transmitted to the coprocessor; EM = 1, the floating point command is simulated by the software simulation.
The TS bit is used to speed up the task, and this purpose is achieved by performing the method of coprocessor switching when necessary. Whenever task switching, the processor sets the TS 1. Ts = 1 When the floating point command will generate an unusable (DNA) exception. The MP bit controls whether the WAIT instruction is generated in TS = 1, whether DNA exception is generated. When MP = 1 and TS = 1, Wait produces an exception; MP = 0, the WAIT instruction ignores TS conditions and does not produce an exception. 3.CR2 and CR3
Control registers CR2 and CR3 are used by the paging management mechanism.
CR2 reports an error message when the page abnormality is generated. When the page abnormality occurs, the processor stores the linear address that causes the page abnormality in CR2. The page exception handler in the operating system checks the contents of CR2, so that which page in the linear address space causes this exception.
CR3 is used to save the physical address of the page directory table. Since the directory is the page alignment, only 20 bits are valid, and the low 12 digits remain unused. When a new value is loaded into CR3, the low 12 bits must be 0; however, from the CR3, the lower 12 bits are ignored. Whenever the value of the CR3 is reset with the MOV command, the contents of the paging mechanism cache can be invalid. In this way, the paging mechanism can be preceded before the Paging mechanism is enabled, that is, the cache of the Paging Machine before the PG position 1 is enabled. The CR3 register can be loaded even if the PG bit or PE bit of the CR0 register or PE bit is 0, and the CR3 can be set in the real mode for initialization of the paging mechanism. When the task is switched, the CR3 is to be changed, but if the value of CR3 in the new task is the same as the value of CR3 in the original task, the processor does not refresh the patch cache so that it has a faster execution speed when the task share also
<2> System Address Register
Global Description Table GDT, local descriptor table LDT and interrupt descriptors Table IDT, etc. are very important segments in protection, which contain important forms used as segments. To facilitate the convenience and quickly positioning these segments, the processor uses some special registers to save the base sites and segment boundaries of these segments. We call these special registers as system address registers.
1. Global Descriptor Table Register GDTR
As indicated by the table starting at this article, the GDTR is 48 in the GDTR, with a high 32-bit site, low 16 bits. Since the GDT does not have a descriptor within the GDT itself, the processor uses GDTR to provide a pseudo descriptor for the special system segment of GDT. GDTR gives GDT as shown below.
The segment boundary in GDTR is limited to bytes. Since there is only 13 bits in the segment selector as a descriptor index, each descriptor is 8 bytes, so it is sufficient to use 16 bits. Typically, the segment definition of the descriptor table containing N descriptors is 8 * n-1.
Using the structural type can define the pseudo descriptor as follows:
PDESC STRUC
Limit DW 0
Base DD 0
PDESC ENDS
2. Local Descriptor Table Register LDTR
The local descriptor table register LDTR specifies the local descriptor table LDT used by the current task. As shown in the table starting at this article, LDTR is similar to the segment register, consisting of a 16-bit register and programmer visible to programmers. In fact, the local descriptor table LDT of each task is a special segment of the system, and is described by a descriptor. The descriptor for the descriptor LDT is stored in the GDT. During the initialization or task switching process, the selection of the descriptor corresponding to the task LDT is loaded into the LDTR, and the processor removes the corresponding descriptor from the GDT according to the selection of the LDTR visible portion, and puts the LDT base Information such as address, boundaries, and attributes save to the invisible cache registers of LDTR. Subsequent access to the LDT, the legality check can be performed according to the relevant information stored in the high speed buffer register.
The LDTR register contains the selection of the LDT of the current task. Therefore, the selection loaded to the LDTR must determine a system segment descriptor in the GDT of the LDT, i.e., the TI bit in the selection must be 0, and the type represented by the type field in the descriptor must be LDT. You can load LDTR with an empty selection, which means that the current task is not LDT. In this case, all selected subsets that are loaded into segments must indicate a descriptor in the GDT, that is, the segment involved in the current task is described by the descriptor in the GDT. If the selection subsection of a TI bit is 1 will be loaded into the segment register, it will cause an exception.
3. Interrupt Descriptor Table Register IDTR
The interrupt descriptor table register IDTR points to the interrupt descriptor table IDT. As indicated by the table starting at this article, the IDTR is 48 bits, of which 32-bit base sites specify the base address of the IDT, and the 16-bit boundary specifies the segment limit of the IDT. Since the 80386 only supports 256 interrupt / abnormalities, the maximum length of the IDT table is 2K, and the paragraph boundary in the byte position is 7FFH. IDTR indicates that the IDT mode is the same as the GDTR indicating GDT.
4. Task status segment register TR
The task status segment register TR contains a descriptor selector indicating the task status segment describing the current task, thereby specifying the status segment of the current task. The format of the task status segment is introduced in the following article. As indicated by the table starting at this article, TR also has programmers visible and not visible. When the selection subsection of the task status segment is loaded into the TR visible portion, the processor automatically saves information such as segment base address in the descriptor indexed in the selection to an invisible high-speed buffer register. After that, access to the current task status segment can be made quickly and convenient. The selector loaded into TR cannot be empty, and must index the descriptor in the GDT, and the type of descriptor must be TSS.
Reference information book name Society Society "80386 and its programming" Tsinghua University Press, Zhou Mingde, editor "80x86 assembly language program design tutorial" Tsinghua University Publishing Social Yang Qiwen Editor
