Verilog-AMS and VHDL-AMS have a new standard for less than 4 years. The modeling language of the hardware behavior, Verilog-AMS and VHDL-AMS are ultrafades of Verilog and VHDL, and Verilog-A is a subset of Verilog-AMS.
The Verilog-AMS hardware description language is 1 subset of Verilog HDL compliant with the IEEE 1364 standard. It covers the definition and semantics of the Verilog HDL recommended by the OVI organization, the purpose of making the designer of the digital-to-mode mixed signal integrated circuit, which can be created and used by the structural description and high-level behavioral description. Therefore, using the Verilog HDL language allows the designer to use different levels of abstraction from different stages of the entire design process (from the analysis of the structural solution until the implementation of the physical device).
Some of the latest technical developments in foreign companies in digital models are listed below:
1. CADENCE combines the new Verilog-AMS standard and different simulation algorithms and the traditional SPICE menu (NetList), such an emulator (ie, spectre) can be different in the design process. Hierarchical application. Cadence also provides Verilog-a language adjustment error tools and graphical user interfaces.
2. APTEQ Design System Company also gives users some model examples when providing their Verilog-A products. Company APTEQ also offers a special Verilog-A insert that allows OVI compatible Verilog-a HDL function blocks to existing Spice simulation environments. The product provides a unified high-performance analog HDL interface through a unique connector solution, allowing it to connect to any SPICE type emulator, ensuring that portable HDL compilation, and it can be correct Evaluate different types of emulator performance. The working mechanism of Verilog-a inserts is to first translate into one intermediate expression by compiling, which can be used by SPICE's hardware description language socket (such as instance) Abstract, parameter setting, loading, and evaluation) are used to run. The insert can provide error, optimization, and anatomical, optimization, and anatomy, such as analog behavior coding. And if you need to simulate, the verification and test of the whole chip, the Verilog-A insert has 1 optional secondary compilation mode that provides high speed, local coding (Native-code) simulation performance.
3, Transcendent Design Technology Company provides Verilog-A / AMS simulation capabilities in its product Transverse. The purpose of this product is to simulate complex electronic mechanical systems, which for some different industrial areas, including automotive industries, aircraft industry, aerospace industry and consumer electronics industry. Transverse supports Verilog-a, new Verilog-AMS language, SPICE, and its model and subcircle, and model written in C language.
