CPU learning notes (1)
Author: Badcoffee
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In April 2005, this is a note in the basic knowledge of hardware. Since the knowledge of this, it has lacks system
Learning, if there is a mistake, please correct it.
First, the main components of Intel CPU:
1. CPU kernel:
It is a truly processor for performing instructions and processing data, which is closely related to the speed of the CPU.
2. l1 cache
The CPU is integrated within the integrated L1 Cache, which is also known as the primary cache, is used to temporarily store partial instructions and data. It and
The CPU is running with frequent frequency, which is the fastest in all Cache. It is generally composed of SRAM, cost is expensive and complicated, due to
The CPU is limited, so the capacity of L1 Cache is generally not too large. CPU's L1 Cache is divided into D-Cache (Data Cache,
Data cache) and ICACHE (Instruction Cache, instruction cache). This dual-channel cache architecture is reduced
Conflicts caused by the cache, effectively improve processor performance. However, the Pentium 4 processor gives up Icache
More efficient T-Cache (Trace Cache).
3. L2 Cache
That is, secondary cache. The cache provides the instructions and data required for the CPU calculation. Usually consisting of three components: L2 Cache
Controller, Cache SRAM and Cache Tag Ram. It is used as a controller, a memory, and a cache search table, respectively.
Due to the cost of L1 Cache, the CPU is integrated to compensate for the L1Cache smaller capacity. L2 Cache
SDRAM is generally selected. At present, the CPU is integrated with L2 Cache, the English is called On-Die, which is generally twice that of L1 Cache or four
Double or even more. In the early days, the second-level cache chip is placed on the motherboard, and the English is ON-BOARD instead of integrating inside the CPU.
4. BSB (Backside Bus):
The backend bus is usually called. Interconnect CPU kernel and secondary cache bus. Mainly responsible for providing instructions stored by L2 Cache to the CPU
And data. The BSB provides three speeds of 66MHz, half speed, and full speed. The BSB speed determines the speed of the CPU to access Cache. Due to the CPU
The required instructions and data are mainly from L2 Cache, so the BSB speed has a very important impact on system performance.
5. FSB (Frontside Bus):
That is, the front end bus is usually said. Interconnect CPU and motherboard chipset bus, generally used to interconnect CPUs and memory controllers.
The speed of FSB is usually said. The high and low of the FSB speed affects the access of the CPU to the main memory.
Second, related nouns:
Frequency:
The CPU accesses the bandwidth of the memory.
Cache line:
.................
Rather Than Reading a Single Word or Byte from Main Memory At A Time, Each Cache Entry IS
USUALLY HOLDS A CERTAIN Number of Words, Known As A "Cache Line" or "Cache Block" and A
Whole Line Is Read and Cached Atce. This Takes Advantage Of The Principle of LocalityOf Reference: IF One Location Is Read The Nearby Location (Particularly Following Locations)
Are Likey to Be Read Soon afterwards. It can also Take Advantage of Page-Mode Dram Which
Allows Faster Access To Consecutive Locations.
Minimum unit of data transfer between main memory and cache. When each CPU accesses memory, request one or more units as cache line
Cache line. Intel's P5 and P6 CPUs, a cache line consists of 32-bytes of data or instructions, that is
Cache line has a total of 256 bits. When the CPU requests 1 cache line to L2 Cache, the 256 digits are transmitted from the BSB to the CPU.
According to or instructions, if the BSB is 64-bit wide, then at least 4 times, if each transmission is completed within 1 clock, then
A Cache Line requires at least 4 clocks; if the BSB data width is 256 bits, simply complete within 1 clock.
Write through:
A cache architecture in which data is written to main memory at the same time as it is cached.
Write back:
.
ATC:
Intel's BSB bus technology called Advanced Transfer Cache referred to as ATC.
MIPS:
MIPS (Million Instructions Per Second) is a representation unit that can perform millions of instructions per second. this is
An outdated and unscientific metric unit of the processor speed and performance.
SSE
The SSE instruction set is Intel's development instruction set for its Pentium III series processor, which includes 8 consecutive data blocks.
Directive, 12 MMX integer operations, and 50 SIMD floating point arithmetic instructions. These instructions can enhance the system to graphics, depending on
Frequency and audio processing. SSE2 adds 144 instructions than the previous generation.
Alu
ALU (Arithmetic Logic Unit, arithmetic logic unit) is part of the CPU to handle all data for mathematical logic.
FPU
The FPU (Floating-Point Unit, floating point arithmetic unit) is a unit that is currently specializing in floating point operations. Before Intel 80486,
FPU is inserted on the motherboard as a specially designed independent chip. It was called a digital collaborative processor or floating point arithmetic processor.
After Intel 80486, the CPU generally built into the FPU.
MMU
MMU (Memory Management Unit, Memory Management Unit) is a system component used to manage virtual memory. MMU is usually a CPU
Part of itself, a small amount of storage space is used to store matching table TLB from virtual addresses to physical addresses (Translation Look-Aside
Buffer, or a cross-conversion table). All data requests are sent to the MMU, which is determined to determine whether the data is within the RAM or a large-capacity storage device.
