Computer motherboard troubleshooting card
Computer Main Board Post Card
Inquiry manual
Sound coding network
A card can be inserted with ISA, or PCI can be inserted
Insert the wrong tank or insert it, the power is not burned any part
Can display crash repeated reset under black screen
No CPU, memory, graphics, etc., one empty motherboard, etc., you can diagnose important signals in the board.
This card uses more than ten chips, the most compatibility is the most compatible, and completely solves the PCI card to "31" and go out of "00" on some motherboards.
I. Overview of the working principle of the diagnostic card is to use the test results of the BIOS internal self-test program in the motherboard, displayed by the code, and the code-sensing quick check table that combines this book can quickly know the computer failure. Especially in the PC cannot boot the operating system, black screen, the speaker is not called, using this card more convenience, so that you have more time. In each of the power circuits, memory, keyboard, video section, hard disk, floppy drive, etc., and analyze the hard disk system configuration, and analyze the configured basic I / O settings, everything is normal. , Boot the operating system. The significant feature is to test key components in the boundary line for the spoke. A key component has a fault enforcement machine transfer to stop, no cursor, the screen does not respond. Then, the non-critical component is tested, and the faulty machine continues to operate, and the present card is inserted into the expansion slot when the display is not displayed. According to the code displayed on the card, refer to which BIOS belongs to your machine, and then find the fault cause and part indicated by this code, you can clearly know the fault.
Second, sixteen-entered character table
Third, diagnostic card parts explanatory diagram
Fourth, indicator function quick check table
The lamp name Chinese meaning should be constant regardless of the ISA or PCI as long as an empty board (no CPU, etc.) is turned on, otherwise the CLK signal is bad. Bios Basic input Output The motherboard is running when there is a read operation on the BIOS. The Irdy master is ready to have an Irdy signal, otherwise it is not bright. OSC oscillates the main oscillator signal of the ISA slot, and the empty board should be constant, otherwise it will stop. The Frame Frame Period The light is flashed when a loop frame signal is turned on, and it is often bright. The RST reset is turned on or pressed for a few seconds. It will be normal. If you do not destroy the reset pin on the motherboard, the acceleration switch or reset circuit is broken. 12V power supply empty plate should be constant, otherwise there is no short circuit in this voltage or motherboard. -12V power supply empty plate should be constant, otherwise there is no short circuit in the voltage or motherboard. The 5V power supply is high on the power supply, otherwise there is no short circuit in the voltage or motherboard. The -5V power supply is always on, otherwise there is no such voltage or motherboard. (Only ISA tank has this voltage) 3v3 power supply This is a 3.3V voltage of the PCI slot. The empty plate should be high, and some of the PCI slots itself has no this voltage, there is no bright.
5. Use flow chart (take the most systematic as an example)
6. Fault code Meaning Quick Version Table Checkscript Read: The Special Code "00" and "FF" and other start codes have three situations: 1 has appeared after a series of other code: " 00 "or" ff ", the motherboard OK. 2 If there is no error in CMOS, the unscrupulous fault does not affect the continuation of the BIOS self-test, and "00" or "ff" will eventually appear. 3 A "00" or "ff" or other start code appears and does not change, it is not running. 2, this table is from small to large sort by code value, and the order in the card is not in order. 3, not listed in the undefined code table. 4. For different BIOS (commonly used ami, award, phoenix) to use the same code to use the same code, it should figure out which type of BIOS you detected, you can check your computer Manual, or directly view on the BIOS chip on the motherboard, or you can see it directly when you start the screen. 5. There is only the previous part of the code, but the ISA slot has a complete self-test code output. And at present, there is currently no code output, and the PCI slot has a complete code output. Therefore, it is recommended that you change this dual slot card to another when viewing the code is not successful. . In addition, the different PCI grooves of the same plate, some slots have a complete code to send, such as the Dell810 motherboard has a complete code display to a PCI slot close to the CPU, change to "00" or "ff", while other grooves come to "38" does not continue to change. 6, the time required for reset signal is not necessarily synchronized with PCI, so it may be ISA to start the code, but the PCI's reset light is not extinguished, so the PCI code is parked on the start code.
Code Award Biosami Biosphoenix BIOS or TANDY 3000 BIOS00. The configuration of the system is displayed; it is about to control Ini19 boot load. .01 processor test 1, processor status verification, if the test fails, the loop is infinite. The testing of the processor register is about to begin, and it is not a mask interrupt. The CPU register test is in progress or failed. 02 Determine the type of diagnosis (normally or manufactured). If the keyboard buffer contains data, it will be invalid. Deactivation cannot be masked; starting through the delay. CMOS write / read out is in progress or fail. 03 Clear the 8042 keyboard controller, issue the TestkBrd command (AAH) power-on delay has been completed. The ROM BIOS checking parts are in progress or fail. 04 Reset the 8042 keyboard controller, verify the testkbrd. Keyboard controller soft reset / power-on test. Tests of programmable interval timers are being conducted or failed. 05 If you continue to repeat the test 1 to 5, an 8042 control state can be obtained. Soft reset / power is determined; the ROM is about to start. The DMA is prepared to be ongoing or failing. 06 To make the circuit for initial preparation, deactivate video, parity, DMA circuit, and clear DMA circuitry, all page registers, and CMOS shutdown bytes. The ROM BIOS check is started, and the keyboard buffer is checked. The DMA initial page register read / write test is in progress or fail. 07 Processor Test 2, verify the work of the CPU register. The ROM BIOS check is normal, the keyboard buffer has been cleared, and the BAT (Basic Assurance Test) command is issued to the keyboard. .08 makes the CMOS timer for initial preparation, the normal update timer's loop. The BAT command has been issued to the keyboard, and the BAT command is about to be written. The RAM update test is in progress or fail. 09EPROM checks sum and must be equal to zero. Verify the basic guarantee test of the keyboard, then verify the keyboard command byte. The first 64K RAM test is underway. 0A makes the video interface initially prepared. Send a keyboard command byte code to write command byte data. The first 64K RAM chip or data line failed, shifted. 0B test 8254 channels 0. Write the keyboard controller command byte, the blocking / unlock command of pins 23 and 24 will be issued. The first 64K RAM odd / even logic failed. 0C test 8254 channel 1. Keyboard controller pin 23, 24 has been blocked / unlocked; the NOP command has been issued. The first 64K RAN address line fault. 0d1, check if the CPU speed matches the system clock. 2. Check whether the control chip has programmed values in accordance with the initial setting. 3, video channel test, if it fails, the horn. The NOP command has been processed; then the CMOS stop register is then tested. The first 64K RAM parity failure 0e test CMOS stop bytes. CMOS stop register read / write test; CMOS check is calculated. Initialize the input / output port address. 0f test extension CMOS. CMOS check summor is calculated; CMOS is initially prepared. .10 test DMA channel 0. CMOS has been initially prepared, and the CMOS status register is about to initially prepare for the date and time. The first 64K RAM 0th position fault. 11 Test the DMA channel 1. The CMOS status register has been initially prepared, which is about to disable DMA and interrupt controllers. The first 64DK RAM first fault. 12 Test the DMA page register. DMA controller 1 and interrupt controllers 1 and 2 are deactivated; the video display is to initiate port B initial preparation. The first 64DK RAM secondary fault. 13 Test 8741 Keyboard Controller Interface. The video display has been deactivated, and the port B has been initially prepared; the input of the board initialization / memory is automatically detected. The first 64DK RAM third bit fault. 14 Test memory update trigger circuit. Circuit initialization / memory automatic detection ends; 8254 timer test is about to begin.
The first 64DK RAM 4th fault. 15 Test the system memory of the beginning of 64K. The second channel timer test is half; 8254 The 2nd channel timer is about to complete the test. The first 64dk Ram fifth fault. 16 Establish an interrupt vector table used in 8259. The second channel timer test ends; 8254 The first channel timer is about to complete the test. The first 64DK RAM 6th fault. 17 Remarks video input / output work, if you install a video BIOS, you are enabled. The first channel timer test ends; 8254 0th channel timer is about to complete the test. The first 64DK RAM seated bit fault. 18 Test video memory, if the installed video BIOS is passed, by bypass. The 0th channel timer test ends; the memory is now updated. The first 64DK RAM 8th fault. 19 Test the interrupt controller (8259) mask bit of the first passage. The memory has been updated and the memory will be completed. The first 64DK RAM ninth fault. 1A Tests the interrupt controller (8259) mask bit of the second channel. The memory update line is being triggered, and will be checked for 15 microsecond / break time. The first 64DK RAM 10th fault. 1b Test the CMOS battery level. Complete the memory update time 30 microsecond test; the basic 64K memory test will be started. The first 64DK RAM 11th fault. 1C Test CMOS check sum. The first 64DK RAM 12th fault. 1D modulates the CMOS configuration. The first 64DK RAM 13th fault. 1E Determination of the size of the system memory and compares it and the CMOS value. The first 64DK RAM 14th fault. 1f test 64K memory to up to 640K. The first 64DK RAM 15th fault. 20 Measuring the fixed 8259 intervals. Start basic 64K memory testing; will test address lines. The subordinate DMA register test is in progress or fail. 21 Maintaining an unmatched interrupt (NMI) bit (parity or inspection of the input / output channel). Through the address line test; it is about to trigger parity. The main DMA register test is in progress or fail. 22 Test 8259 Interrupt function. End Trigger parity; will start serial data reading / write test. The main interrupt shield register test is in progress or fail. 23 Test protection mode 8086 virtual way and 8086 page mode. Basic 64K serial data read / write test is normal; any adjustment before the interrupt vector initialization is started. The slave interrupt shield is tested or failing. 24 Determine 1 MB of extended memory. Any adjustment before the vector initialization is completed, and the initial preparation of the interrupt vector is started. Set the ES segment address register registry to the high end of the memory. 25 Test all memory after a 64K. Complete the interrupt vector initial preparation; the input / output port of the 8042 is started for the rotation type. Putting the interrupt vector is ongoing or failing. 26 Exceptions of test protection methods. Read the input / output port of 8042; it is about to initially prepare the global data for the rotation type. Turn on the A20 address line; let it participate in addressed. 27 Determine the control or blocking of the ultra-cache memory. All 1 data initial preparation ends; any initial preparation after the interrupt vector will be performed. Keyboard controller test is in progress or fail. 28 Determine the control or special 8042 keyboard controller of the ultra-cache memory. The initial preparation after the interrupt vector is completed; the monochrome method is about to be modified. CMOS power failure / check summing is in progress. 29. Monochrome mode has been scheduled, and the color mode is about to be modified. Check for CMOS configuration validity is underway. 2A makes the keyboard controller for initial preparation. The color method has been modified, and the trigger parity before the ROM test is performed. Set up the 64K basic memory. 2b The disk drive and controller are initially prepared. Trigger the end of the parity; any adjustment required to control the optional video ROM check. The screen memory test is in progress or fail. 2C Check the serial port and make it initially prepared. Complete the processing before the video ROM control; the optional video ROM is about to be viewed. The screen is initially prepared or failing.
2D detect parallel ports and make it initially prepared. The optional video ROM control has been completed, and the control of any other processing after video ROM replies control is performed. The screen scales test are in progress or fail. 2E The hard disk drive and controller are initially prepared. Repeated from the video ROM control; if the EGA / VGA is not found, the display memory read / write test is performed. The video ROM is underway. The 2F detects the mathematical coordinator and makes it initially prepared. No EGA / VGA was found; the display memory read / write test is now started. .30 creates basic memory and expansion memory. Read / write test by display memory; It is considered that the screen is working. 31 Detection of the selected ROM from C800: 0 to EFFF: 0, and makes it initially prepared. The display memory read / write test or scan check failed, and another display memory read / write test is performed. Monochrome monitors are workable. 32 Programming of I / O chip on the motherboard COM / LTP / FDD / sound device makes it suitable for setting values. Read / write test by another display; another display scan check is performed. The color monitor (40 columns) can work. 33. The video display check is ended; the configuration of the adjustment switch and the actual plug-in test display will begin. Color monitor (80 columns) is workable. 34. The display adapter has been verified; the display mode will then be scheduled. The timer tick interrupt test is in progress or fail. 35. Complete the modulation display method; the data area of the BIOS ROM will be checked. The shutdown test is in progress or fail. 36. The BIOS ROM data area has been checked; the cursor of the power-on information is scheduled. A-20 fails in the door circuit. 37. The cursor adjustment of the identification of power-on information has been completed; Unexpected interruption in the protection mode. 38. Complete the display of power-on information; will read the new cursor position. RAM test is in progress or address fault> FFFFH. 39. The location of the saved cursor has been read, and the reference information string is about to be displayed. .3a. The reference information string is displayed; it is about to display
47. The page is about to be written in the extended memory; the basic 640K memory is written to the page. .48. The basic memory has been written to the page; the memory is about 1MB or more. Video check, CMOS reconfiguration. 49. Find 1BM or less memory and test; the memory is about 1MB or more. .4a. Find 1MB of memory and test; will be checked for the BIOS ROM data area. Initialize the video. The 4B.BIOS ROM data area is over, which is about to check
80. The keyboard test begins, is cleared and checked whether there is a key card, which is about to restore the keyboard. Turn off the programmable input / output device. 81. Find the keyboard recovered in the keyboard; the test command of the keyboard control port will be issued. .82. Keyboard controller interface test ends, will be written to the command byte and make the circular buffer be initially prepared. Detect and install the fixed RS232 interface (serial port). 83. The command byte has been written, and the initial preparation of global data has been completed; if there is no key lock. .84. That has been checked to check if the memory is missing with CMOS. Detect and install the fixed parallel port. 85. The size of the memory has been checked; the flexible error and password or bypass arrangement are already displayed. .86. The password has been checked; the programming beforepassing bypass arrangement is. Reopen the programmable I / O device and detect if fixed I / O conflicts. 87. Complete programming before the arrangement; CMOS schedule will be performed. .88. Remove the clear screen from the CMOS scheduler; will be programmed. Initialize the BIOS data area. 89. Complete the scheduled programming; the power-on screen information is about to display. .8a. Display a screen information. Perform expansion BIOS data area initialization. 8b. Show information: The main and video BIOS will be masked. .8c. Successfully shielded the main and video BIOS, the programming of the Arrangement option after CMOS will begin. Perform the floppy drive controller to initialize. 8D. It has been scheduled for programming, and then checks the mouse and performs initial preparation. .8E. Detected a mouse and completed the initial preparation; the hard disk is reset. .8f. The soft disk has been checked, which will be initially prepared, subsequently equipped with a soft disk. .90. The end of the soft disk configuration; the existence of the hard disk will be tested. The hard disk controller is initialized. 91. The hard disk has the end of the test; the hard disk is then configured. The local bus hard disk controller is initialized. 92. Hard disk configuration is completed; the data area of the BIOS ROM is about to check. Jump to the user path 2.93. The data area of the BIOS ROM has been checked; continues. .94. The data area of the BIOS ROM is completed, that is, the size of the basic and expanded memory is modulated. Turn off the A-20 address line. 95. Adjust the size of the memory is adjusted in response to the mouse and the hard disk 47; it is about to verify the memory. .96. Check the recovery of the memory; the initial preparation before the C800: 0 is optional. "ES section" registry cleared. 97.C800: 0 Any initial preparation before the ROM control ends, followed by inspection and control of the optional ROM. .98. The control of the optional ROM is completed; any processing required after an optional ROM reply control is performed. Find ROM selection. 99. Any initial preparation required after the ROM test is completed; the data area of the timer or the basic address of the printer will be established. .9a. The return operation after the timer and the printer basic address are modulated; that is, the RS-232 basic address is scheduled. Shield ROM selection. 9b. Return after the basic address of the RS-232; the initial preparation of the coprocessor test is now performed. .9c. The initial preparation required before the coordinator test is completed; then the coprocessor is initially prepared. Establish power save management. 9D. Coprocessor is initially prepared, any initial preparation after the coprocessor test. .9E. Initial preparation after completing the coprocessor, the extended keyboard, keyboard identifier, and digital locking will be checked. Open hardware interrupt. 9f. The extended keyboard has been checked, the identification flag, the digital lock is turned on, or the keyboard recognition command will be issued. .A0. Send a keyboard recognition command; will soon recover the keyboard identification mark. Set time and date. A1. Keyboard recognition mark recovery; followed by a high speed buffer test. .A2. The cache test ends; it is about to display any soft errors. Check the keyboard lock. A3. Soft error is displayed; the rate of the keyboard strike will be scheduled. .A4. Adjust the hit rate of the keyboard, the waiting state of the memory will be developed. The keyboard repeats the initialization of the input rate.
