First, data transmission instructions
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They transmit data between the memory and registers, registers, and input and output ports.
1. Universal data transfer command.
MOV transmits or bytes.
Movsx first symbol extension, then transfer.
Movzx first zero extension, then transfer.
Push the word into the stack.
Pop put the word stack.
Pusha presses the AX, CX, DX, BX, SP, BP, SI, DI into the stack.
POPA pops up DI, SI, BP, SP, BX, DX, CX, and AX places the stack.
Pushad presses Eax, ECX, EDX, EBX, ESP, EBP, ESI, and EDI press sequence into the stack.
Popad pops up EDI, ESI, EBP, ESP, EBX, EDX, ECX, and EAX pops up the stack.
BSWAP switches the order of the bytes in 32-bit registers
XCHG swap word or bytes. (At least one opera is register, segment registers can not operate as an operand)
CMPXCHG compares and exchanges the operand. (The second operand must be accumulator Al / Ax / Eax)
XADD is swapped first. (The result is in the first operation)
XLAT byte check table conversion.
─ BX pointing to a 256-byte table starting point, Al is the index value of the table (0-255, ie
0-ffh); return AL is the results of the surfaction table. ([BX Al] -> Al)
2. Enter the output port transfer command.
IN I / O port input. (Syntax: in accumulator, {port number │DX})
OUT I / O port output. (Syntax: OUT {port number │DX}, accumulator)
When the input output port is specified immediately, its range is 0-255; when the register DX is specified,
Its range is 0-65535.
3. Destination address transfer command.
LEA is loaded into a valid address.
Example: Lea DX, String; exist offset addresses to DX.
The LDS transmits the target pointer and puts the pointer content into the DS.
Example: LDS Si, String; Deposit Segment Address: Offset Address to DS: Si.
LES transmits the target pointer and puts the pointer content into the ES.
Example: LES DI, STRING; Putting Segment Address: The Offset Address is stored in ES: DI.
LFS transmits the target pointer and puts the contents of the pointer into the FS.
Example: LFS Di, String; Put the segment address: Offset Address to FS: DI.
LGS transmits the target pointer and puts the contents of the pointer into the GS.
Example: LGS Di, String; Deposit Segment Address: Offset Address to GS: DI.
The LSS transmits the target pointer and puts the pointer content into SS.
Example: LSS DI, STRING; Deposit Segment Address: The Offset Address is SS: DI.
4. Sign Transfer Directive.
The LAHF flag register is transmitted, and the flag is loaded into AH.
SAHF logo register transmits, put the AH content to the flag register.
Pushf sign is in the stack.
Popf logo putting the stack.
Pushd 32-bit flag is in the stack.
Popd 32 bit sign out.
Second, arithmetic operation instructions
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Add add.
ADC carries a carry.
INC plus 1.
AAA adds ASCII code adjustment.
DAA adding decimal adjustment.
SUB subtraction.
SBB belt borrowing subtraction.
Decimal 1.
NEC is reversed (decreased by 0).
CMP comparison. (Two Operations subtilion, only modify the flag, no return results).
AAS subtraction ASCII code adjustment.
DAS subtraction of decimal adjustment.
Mul No symbol multiplication.
IMUL integer multiplication.
The above two, the result is sent to AH and Al (byte operation), or DX and AX (word operation),
AAM multiplication ASCII code adjustment.
Div no symbol division.
IDIV integer division.
The above two, the results are sent:
Commercial feed al, the remainder is back to AH, (byte operation);
Or quotient back to AX, the remainder is sent to DX, (word operation).
AAD division ASCII code adjustment.
The CBW byte is converted to the word. (Extension the symbol of the AL to AH)
The CWD word is converted to double words. (Extended the symbols in the AX to DX)
The CWDE word is converted to double word. (Extend the word symbol in the AX to Eax)
CDQ double word extension. (Extends the symbols in Eax to EDX)
Third, logical operation instruction
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AND and operations.
OR or calculation.
XOR is too or operator.
NOT reflects.
Test test. (Two operations and operations, only modify the flag, no return results).
SHL logic left shift.
SAL arithmetic left shift. (= SHL)
SHR logic moves right.
SAR algorithography right shift. (= SHR)
Rol loop left shift.
ROR loop right shift.
The RCL is left left by the transvented cycle.
RCR is shifted by the loop of the carry.
The above eight shift instructions, the number of shifts can reach 255 times.
When shifting once, you can use the operation code directly. Such as SHL AX, 1.
Shift> 1 time, the number of shifts is given by the register CL.
Such as MOV CL, 04
SHL AX, CL
Fourth, string instructions
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DS: Si source segment register: source string address.
ES: DI Target Series Segment Register: Target String Address.
CX repeat count counter.
Al / AX scan value.
D Sign 0 indicates that Si and Di should be automatically incremented in repetitive operations; 1 indicates automatic reduction.
The z flag is used to control the end of the scan or compare operation.
MOVS string transfer.
(MOVSB transfer character. Movsw transfer word. Movsd transmits double word.)
CMPS string comparison.
(CMPSB compare characters. CmpswsW comparison word.)
SCAS string scanning.
Comparing the contents of Al or AX with the target string, the comparison results are reflected in the flag.
LODS is loaded.
Put the elements (words or bytes) in the source string into Al or AX.
(LODSB transfer characters. LODSW transmits word. Lodsd transmits double word.)
STOS Save the string.
Is the reverse process of LODS.
Rep when CX / ECX <> 0 is repeated.
REPE / REPZ is equally equal to ZF = 1 or compared, and CX / ECX <> 0 is repeated.
Repne / RepNZ is repeated when ZF = 0 or comparison results is equal, and CX / ECX <> 0 is repeated.
REPC is repeated when CF = 1 and CX / ECX <> 0.
REPNC is repeated when CF = 0 and CX / ECX <> 0.
V. Program Transfer Directive
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1> unconditional transfer command (long transfer)
JMP unconditional transfer instruction
Call process call
The RET / RETF process is returned.
2> Condition transfer instruction (short transfer, -128 to 127)
(When only (sf xor of) = 1, OP1 JA / JNBE is not less than or does not equal time transfer. JAE / JNB is greater than or equal to transfer. JB / JNAE is smaller than the transfer. JBE / JNA is less than or equal to transfer. The above four, test the result of unsigned integer operations (markers C and Z). JG / JNLE is greater than the transfer. JGE / JNL is greater than or equal to transfer. JL / JNGE is smaller than the transfer. JLE / JNG is less than or equal to transfer. The results of the above four, test band symbol integer operations (markers S, O and Z). JE / JZ is equal to the transfer. JNE / JNZ is not equal to time transfer. The JC is transferred when it is in. JNC is transferred when it is carry. JNO is transferred when it is overflow. JNP / JPO parity is transferred when odd. The JNS symbol bit is transferred when "0". JO overflow transfer. JP / JPE parity is transferred when an even number. The JS symbol bit is transferred when "1". 3> Cycle Control Directive (Short Transfer) LOOP CX is not a zero cycle. Loope / Loopz CX is not zero and logo z = 1 cycle. Loopne / loopnz CX is not zero and log z = 0 cycles. JCXZ CX is zero transfer. JECXZ ECX is transferred to zero. 4> Interrupt Directive INT interrupt instruction INTO overflow interrupt IRET interrupt return 5> Processor Control Directive The HLT processor is suspended until an interrupt or reset signal appears. WAIT When the chip lead Test is high, the CPU enters the waiting state. ESC is converted to the outer processor .lock blockbus. NOP empty operation. The STC is placed in place flag. CLC inlet marker. CMC carry mark reflects. STD direction flag. CLD cleaving flag. STI sets the interrupt allowed bit. CLI clear interrupt allowed bit. Six, pseudo-instructions ────────────────────────────── DW definition word (2 bytes). The ProC definition process. The ENDP process ends. Segment definition segment. Assume setting segment register addressing. Ends end. End program ends. 8088 assembly jump CMP A, B Compare A and B MOV A, B send B value to a Ret returns the main program NOP has no effect, English "No Operation" is short, meaning "do nothing" Call call subroutine Jum is jumped if JE or JZ is equal JN or JNZ is not equal JMP unconditional jump JB is jumped if it is smaller than Ja is greater than JG is greater than JGE is greater than or equal to jump JL is jumping if it is smaller than Jle is less than or equal to POP outlet Push stack MOV Function: Give the source operand to the destination operand Syntax: MOV destination operand, source operand Format: MOV R1, R2 MOV R, M MOV M, R Mov R, Data XCHG Function: Switch data for two operands Grammar: xchg Format: XCHG R1, R2 XCHG M, R XCHG R, M Push, POP Function: Press the operand into or remove the stack Syntax: PUSH Operations POP Operation Format: Push R Push M Push Data Pop R POP M Pushf, POPF, Pusha, POPA Function: Stack instruction group Format: Pushf POPF Pusha Popa LEA, LDS, LES Function: Take the address to the register Grammar: Lea R, M LDS R, M Les R, M XLAT (XLATB) Function: Check Data Instructions Grammar: XLAT XLAT M Calculation instruction Add, ADC Function: addition instruction Syntax: Add OP1, OP2 ADC OP1, OP2 Format: Add R1, R2 Add R, M Add M, R Add R, Data Impact markers: C, P, A, Z, S, O SUB, SBB Function: subtraction instruction Syntax: SUB OP1, OP2 SBB OP1, OP2 Format: SUB R1, R2 SUB R, M SUB M, R SUB R, DATA SUB M, DATA Impact markers: C, P, A, Z, S, O INC, DEC Function: add one or minus the value of the OP Syntax: IncOP Dec OP Format: incr / m DEC R / M Impact markers: P, A, Z, S, O NEG Function: reverse the symbol of the OP (take binary complement) Syntax: NEG OP Format: NEG R / M Impact markers: C, P, A, Z, S, O Mul, Imul Function: Multiplication Syntax: MUL OP IMUL OP Format: MUL R / M IMUL R / M Impact markers: C, P, A, Z, S, O (only IMUL will affect S flag) Div, IDIV Function: division instruction Syntax: DIV OP IDIV OP Format: DIV R / M IDIV R / M CBW, CWD Function: Symbolic number expansion instruction Grammar: CBW CWD AAA, AAS, AAM, AAD Function: Non-pressure BCD code operation adjustment instruction Grammar: AAA AAM AAD Impact markers: A, C (AAA, AAS) S, Z, P (AAM, AAD) DAA, DAS Function: Compressed BCD code adjustment instruction Grammatical: DAA DAS Impact markers: C, P, A, Z, S Binover instruction set And, OR, XOR, NOT, TEST Function: Execute the logical operation between BIT and BIT Syntax: And R / M, R / M / DATA or R / M, R / M / DATA XOR R / M, R / M / DATA TEST R / M, R / M / DATA NOT R / M Effect Sign: c , O, P, Z (where C and O two flags will be set to 0) NOT instructions do not affect any logo SHR, SHL, SAR, SAL Function: shift instruction Syntax: SHR R / M, DATA / CL SHL R / M, DATA / CL SAR R / M, DATA / CL SAL R / M, DATA / CL Impact markers: C, P, Z, S, O ROR, ROL, RCR, RCL Function: loop shift instruction Syntax: R / M, DATA / CL ROL R / M, DATA / CL R / M, DATA / CL RCL R / M, DATA / CL Impact markers: C, P, Z, S, O Process Control Instruction Set CLC, STC, CMC Function: Set the carry mark Grammar: CLC STC CMC Sign: c CLD, STD Function: Setting direction flag Grammar: CLD STD Sign: d CLI, STI Function: Set the interrupt flag Grammar: CLI STI Sign: i CMP Function: Compare the value of OP1 and OP2 Grammar: CMP R / M, R / M / DATA Sign bit: C, P, A, Z, O JMP Function: Jump to the specified address execution Syntax: JMP address JXX Function: When a particular condition is established, jump to the specified address execution Grammar: JXX address Note: A: Above, when c = 0, Z = 0 is established B: BELOW, is established when c = 1 C: Carry, is established when the CXZ: the value of the CX register is 0 (ZERO) E: Equal, is established when z = 1 G: Greater (greater than), when z = 0 and S = 0 L: Less (less than), when S is not zero N: NOT (reverse conditions), need to use other symbols O: Overflow, o = 1 is established P: Parity, P = 1 PE: PARITY EVEN, P = 1 PO: PARITY ODD, P = 0 is established S: Sign, S = 1 is established Z: ZERO, Z = 1 Loop Function: Cycle instruction set Syntax: loop address Loope (z) Address loopne (z) address Sign bit: no Call, Ret Function: subroutine call, return instruction Syntax: Call address RET N Sign bit: no Int, IRet Function: Interrupt call and return instruction INT N IRET Save: When Int is executed, the CPU will automatically enter the value of the flag register, and the flag value in the stack is bounted back to the register in the execution IRET. String operation instruction set Movsb, Movsw, Movsd Function: String Transfer Directive Grammar: Movsb Movsw Movsd Sign bit: no CMPSB, CMPSW, CMPSD Function: String Compare Directive Syntax: CMPSB CMPSW CMPSD Sign bit: C, P, Z, S, O ScaSB, Scasw Function: String Search Instruction Syntax: scaSB scASW Sign bit: C, P, Z, S, O Lodsb, lodsw, stosb, stosw Function: String Load or Storage Directive Syntax: Lodsb Lodsw Stosb Stosw Sign bit: no REP, REPE, RepNE Function: Repeated prefix instruction set Syntax: REP instruction S REPE instructions S Repne command S Sign bit: Depending on the instruction S
