In ISE series software, the implementation of CPLD / FPGA design mainly includes several aspects of translate, mapping (MAP), Place & Route and Time Parameter Extract (TIMING).
Conversion
During the conversion process, multiple design files and constraint files will be merged into an NGD file and output a BLD file at the same time. Among them, the NGD file contains all logical descriptions of the currently designed, and the run report when the BLD file is converted. Convert Acceptable Design files include end, edf, edif, and sedif files, converted constraints include UCF, NCF, MNC, and NGC files.
2. Mapping
During the mapping process, the currently designed NGD file will be mapped to a specific physical unit of the target device (e.g., CLB, IOB), and saved in the NCD file. The mapping input files include NGD, NMC, NCD (optional), and MFP (optional), and output files include NCD, PCF, NGM, and MRP files. Among them, the MFP file is a layout constraint file generated by the FLOORPLANER. The NCD file contains the currently designed physical mapping information. The PCF file contains the currently designed physical constraint information. The NGM file is related to the currently designed static timing analysis, the MRP file is the mapping operation report. The MRP file mainly includes mapping command parameters, logical resources occupied by target design, error and warnings in the mapping process, logic deleted in the optimization process, the IOB resource content occupied in the target design.
3. Layout wiring
By reading the currently designed NCD file, the layout wiring places and connects the physical unit generated by the map on the target device and extracts the corresponding time parameters. The input file of the layout wiring includes NCD, PCF, and NCD (optional) template files, and output files include NCD, DLY, PAD, and PAR files. In the output file of the layout wiring, the NCD file contains all physical implementation information of the currently designed, the DLY file contains the currently designed network delay information, the PAD file contains the currently designed I / O pin configuration information, the PAR file is the layout wiring Release report. PAR files mainly include command line parameters of layout wiring, errors and warnings in layout wirings, resource occupied by target design, for wiring network, network timing information, etc.
4. Time parameter extraction
The time parameter extraction generates the currently designed return network table, which will be used for timing simulation. The input file extracted by the time parameter includes NCD and PCF (optional) files. The timing report of the time parameter extraction output can reflect whether the current design meets the timing constraint.
