Recently, product vendors are increasingly using the FPGA implementation of the ASIC (Application Specific Integrated Circuit Specific Use Integrated Circuit). Although it is expected to shorten the development cycle, reduce the ASIC development cost, but there is a cost when using the microcontroller. And an increase in power consumption. Altera claims to solve the above topics and have been promoting Nios.altera, which can be packaged in FPGA, has four products that have different performance and circuit scale. They are pursuit of high performance "Nios II / FFAST" - with higher performance and medium FPGA usage; "Nios II / E ECONOMY" for pursuing circuit scale, the performance is general, and the amount of FPGA is also low; And "Nios / SSTANDARD" between the performance and circuitry is between two - high performance and low FPGA usage. Using a soft core processor in FPGA is more advantageous than hard core, because hard flexibility is poor, the latest technology is usually unable to use. As the system is increasingly advanced, the standard processor-based program will be eliminated, while the Nios II processor's scheme is based on HDL source code, which can be modified to meet new system requirements, and will not be eliminated. Implement the processor in the form of an HDL IP core, developers can completely customize CPUs and peripherals to obtain processors with demand. The NIOS II processor is positioned to 90 nm Stratix II or Cyclone II device, which can achieve optimal performance by adopting the latest FPGA technology. At the same time, the NIOS II embedded processor series adopts a new architecture, which has a higher level of efficiency and performance than the first generation NIOS. Compared with the first generation of processors, Nios II nuclear averages less than 50% of FPGA resources are calculated.
Dedicated instruction implementation structure block diagram in NIOS II CPU
Nios II achieves performance and prices in Altera all FPGA
In order to improve system performance, the NIOS II processor supports 256 dedicated instructions with fixed or variable clock cycle operations, and designers can use these instructions to accelerate the strict code segment. These dedicated instructions allow the designer to implement a large-computational amount in the hardware, which "calls" as the C language subroutine. In contrast, the original NIOS processor only supports 5 dedicated instructions, each executing the number of clock cycles that must be determined each time. Altera said although some processor cores facing ASIC provide dedicated instructions and / or hardware accelerators, it is not possible to quickly provide operationally deliverable silicon flakes like the NIOS II processor.
