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Summary: From the nature of digital system design, combine the currently developed chip system, comparison, research various hardware description languages; detail the development history, architecture and design methods of various languages; explore the development trend of future hardware description language At the same time, for the state of domestic EDA foundation, some beneficial thinking is made in hardware description languages.
Keywords: ASIC hardware Description Language HDL Verilog HDL VHDL Systemc SuperLog Chip System SOC
Language Hardware Description Language HDL is a language to describe digital circuits and systems using a formal method. With this language, the design of the digital circuitry can describe its design idea from the upper to the lower layer (from abstraction to specific), with a series of hierarchical modules to represent an extremely complex digital system. Then, the electronic design automation (EDA) tool is used, and the simulation verification is performed layer by layer, and then the module in which it needs to be changed, and the automatic integrated tool is converted to the gate-class circuit network. Next, use a dedicated integrated circuit ASIC or field programmable gate array FPGA to automatically lay out the wiring tool, and convert the menu to the specific circuit wiring structure to be implemented.
At present, this high-level-design approach has been widely used. According to statistics, there are currently more than 90% of the US Silicon Valley to design hardware description languages.
Hardware Description Language HDL has been more than 20 years of history, and successfully applied to various stages of design: modeling, simulation, verification, and synthesis. By the 1980s, hundreds of hardware descriptions have emerged, which have played great promotion and promotion of design automation. However, these languages are generally facing specific design areas and hierarchies, and many languages make users at a loss. Therefore, it is urgent to design a multi-domain, multi-level and universally identified standard hardware description language. In the late 1980s, VHDL and Verilog HDL language adapted to this trend, and it became the IEEE standard.
Now, with the emergence of system-level FPGAs and system chips, hardware and software coordination design and system design become more important. Hardware design in the traditional sense is increasingly incorporated in combination with system design and software design. Hardware description languages are adapted to new situations, develop rapidly, have a lot of new hardware description languages, like SuperLog, Systemc, Cynlib C , and more. Which language is selected, and the entire industry is conducting a fierce discussion. Therefore, it is entirely necessary to make some comparative studies in this regard, and do some meaningful work for EDA design, and also make the foundation for developing our future chip design technology.
1 Currently HDL development
At present, the hardware description language can be described as a hundred flowers, VHDL, SuperLog, Verilog, Systemc, Cynlib C , C Level, and more. Although the various languages have their own strengths, the industry is designed to use which language used, but is what is hard to agree.
More consistent opinions are that HDL and C / C languages have their own martial arts in design processes. The problem appears in the system level and implementation level: When will I stop using a language in use, and start using another language? Or just use a language directly? It seems that it seems to have been more time.
At the International HDL meeting held in 2001, participants used what design language used a vivid and fierce debate. Finally, attendees vote: If you want to launch a chip design project, which solution they are willing to choose? As a result, only 2 votes or 3 votes in favor of using Systemc, Cynlib and C Level design; and SuperLog and Verilog have about 20 ticket. As for the situation, even the meeting moderator John Cooley also clearly said: "After 5 years, no one knows what this planet will happen." The people who believe in Verilog think that development The new design language is a waste; the SYSTEMC defender believes that the complexity of the system-level chip SOC quickly needs a new design method; the praise of the C language believes that Verilog is the assembly language of hardware design, and the programming standard is very It will be a high-level language. Cynlib C is the best choice. It is fast, the code is streamlined; SuperLog's defenders believe that Superlog is Verilog extension, only one language and an emulator can be provided throughout the design process. Compatible with existing methods is an evolution, not a revolution.
Of course, all the above discussions have not mentioned simulation design. If you want to design a chip with an analog circuit, the hardware description language must have analog extension, like Verilog HDL-A, which requires both the gate-class switch-level, and requires the ability to describe physical properties.
2 representative HDL languages
2.1 VHDL
As early as 1980, because the US military industry needs to describe the method of electronic systems, the US Department of Defense began to develop VHDL. In 1987, the IEEE (Institute of Electrical and Electro- NICS Engineers) set VHDL as a standard. The reference manual is the IEEE VHDL Language Reference Manual Tandle 1076 / B version of 1987, called IEEE 1076-1987. It should be noted that the initial VHDL is only a standard for system specifications, rather than designing. The second version is developed in 1993, called VHDL-93, adding some new commands and properties.
Although there is "VHDL is a $ 400 million mistake", VHDL is the only hardware description language that has been developed as a standard in 1995, which is the facts and advantages of it; but it is really troublesome, and it is The integrated library has not been standardized so far, and does not have the description capability of transistor opening levels and the description of simulation design. The current view is that VHDL is more suitable for the design of a large-scale system-level digital circuit.
In essence, the underlying VHDL design environment is supported by the device library described by Verilog HDL, therefore, the interoperability between them is very important. At present, both international organizations of Verilog and VDHL OVI, VI are planning this job, preparing to set up a special working group to coordinate interoperability between VHDL and Verilog HDL languages. Ovi also supports no translation, free expressions from VHDL to Verilog.
2.2 Verilog HDL
Verilog HDL is in 1983, the Phil Moorby of GDA (GATEWAY Design Automation). Phil Moorby later became the main designer of Verilog-XL and the first partner of Cadence. In 1984 to 1985, Phil Moorby designed the first emulator called Verilog-XL; in 1986, he made another huge contribution to the development of Verilog HDL: proposed to use the fast-level simulation. XL algorithm. With the success of the Verilog-XL algorithm, Verilog HDL language has developed rapidly. In 1989, Cadence acquired GDA, Verilog HDL language became private property of Cadence. In 1990, Cadence decided to disclose the Verilog HDL language, which has established OVI (Open Verilog International organization, responsible for promoting the development of Verilog HDL language. Based on the superiority of Verilog HDL, IEEE has developed Verilog HDL IEEE standard in 1995, which released Verilog HDL 1364-2001 standard in 2001. In this standard, the Verilog HDL-A standard has been added to enable Verilog's ability to simulate design description.
2.3 SuperLog Develop a new hardware design language, there is always some adventures, but may not be able to take advantage of the experience of hardware development. Can you expand a new system-level design language standard in combination with the characteristics of language C, C or even Java, etc.
Superlog is developed in such a background system-level hardware description language. Verilog language's first hardware description language expert in Phil Moorby and Peter Flake, working in EDA called Co-Design Automation to begin extension of Verilog. In 1999, Co-Design released the SuperLogTM system design language and issued two development tools: SystemsimTM and SystemExtM. One for system-level development, one for advanced verification. In 2001, Co-Design has released the SuperLog extended subset ESS to the Electronics Industry Standardization Organization, which can provide more level hardware integrated abstraction, based on today's Verilog language RTL-level integrated subset, Used for various system-level EDA software tools.
So far, more than 15 chip design companies have developed chip design and hardware development with Superlog. Superlog is a system-level hardware description language with good prospects. But not long ago, due to the landslide of the IT industry, Co-Design has become more confusing by Synopsys, and the situation becomes confusing.
2.4 Systemc
With the rapid development of semiconductor technology, SOC has become the development direction of today's integrated circuit design. In various design of the system chip, the system definition, hardware and software division, design implementation, etc., the integrated circuit design industry has always considering how to meet the SOC design requirements, which has been looking for software and hardware descriptions that can simultaneously achieve higher levels. System-level design language. In this case, SystemC is developed by Synopsys and Coware to develop in the current demand for system-level design languages. On September 27, 1999, more than 40 world famous EDAs, IP companies, semiconductor companies and embedded software companies announced its establishment "Open SYSTEMC Alliance." The famous company Cadence has also joined the SYSTEMC Alliance in 2001. SYSTEMC started to update the 0.9 version of the initial in the early stage of the Union in September 1999, from version 1.1, until the latest version 2.0 until October 2001. 3 System structure and design methods for various HDL languages
3.1 Systemc
All Systemc is based on C ; the upper framework in Figure 1 is clearly based on the next layer; the SystemC kernel provides a module for system architecture, parallel, communication, and synchronous clocks; fully supporting kernel Data types, user-defined data types; usual communication methods, such as signals, FIFOs, can be established on the basis of the kernel, and the calculation modules often used can also be built on the kernel; if needed, Figure 1 is more The low-level content can be used directly without relying on the upper layer. In actual use, SystemC consists of a set of description libraries and a library containing the simulation kernel. In the user's description program, you must include the corresponding class library, which can be compiled by the usual ANSI C compiler. SYSTEMC provides software, hardware, and system modules. Users can freely choose at different levels, build their own system model, simulation, optimization, verification, synthesis, etc.
3.2 Superlog
Superlog gathered the characteristics of Verilog, powerful, functional verification, and system-level structural design, is a high-speed hardware description language. Its architecture is shown in Figure 2.
1 Verilog 95 and Verilog 2K. Superlog is a super-collection of Verilog HDL, supports the latest Verilog 2K hardware model.
2 C and C languages. Superlog provides a C language structure, type, pointer, and features C facing objects.
3 Superlog extension integrated subset ESS. ESS provides a new integrated abstraction level for hardware description.
4 powerful verification. Automatic test benchmark, such as random data generation, functional coverage, various proprietary checks, etc. Superlog's system-level hardware development tools mainly include CO-Design Automation's SystemSimTM and SystemExTM, while developing in conjunction with other EDA tools.
3.3 Verilog and VHDL
These two languages are traditional hardware description languages, and there are many books and materials to view reference, not much here.
4 currently available feasible strategies and ways
According to the traditional method, we divide the model type of the hardware abstraction class into the following five: ◇ System-level (System) - the model to implement the model of the algorithm with the high-level structure provided by the language;
◇ Algorithm - Model for operating the algorithm with the advanced structure provided by the language;
◇ RTL Level (Register Transfer Level) - Describe the flow of data between registers and how to process, controlling these data flows. (The above three belong to behavioral description, only RTL levels have clear correspondence with logic circuits.)
◇ Gate-Level - Describe the connection model between logic gates and logic gates. (There are exact connection with logic circuits. The above four, digital system design engineers must master.) ◇ Switch-level - Describe the model of the triode and storage nodes in the device and the models thereof. (There is corresponding relationship with specific physical circuits, process library components and macro sector designers must master.)
According to the development trend of the current chip design, the verification level and integrated abstraction level may also become a standard level. Because they are suitable for IP core multiplexing and system-level simulation integrated optimization, software (embedded, firmware) is increasingly related to the systematic abstraction level.
Currently, for a system chip design project, the solutions that can be employed include the following:
1 The most traditional way is that VHDL is adopted in the system level, and the C language is used in the software level, and Verilog is adopted at the real level. At present, the interoperability of VHDL and Verilog has gradually been standardized, but the coordination design of software and hardware is still a very challenging job because software is increasingly the key to SOC design. The program features a small risk, a large integrated difficulty, is fully compatible with the original approach, and has a ready-made development tool; but the tool integration is done by the developer.
2 System-level and software stages use SuperLog, hardware levels, and implementation, using Verilog HDL description, which is compatible with the original hardware design. Just re-purchase two superLog development tools SystemsimTM and SystemExtM. The program is characterized by a small risk, easy to integrate, compatible with the original hardware design, and has an integrated development environment.
3 The system-level and software level uses Systemc, hardware-level uses Systemc with regular Verilog HDL transitions, which is fully compatible with the original software compilation environment. Developers only need a set of description libraries and a library containing the simulation kernel, you can develop in the usual ANSI C compiler environment; but hardware description is completely incompatible with the original approach. The program is characterized by a large risk, which is well-compatible with the original software development, and hardware development is risky. 5 future development and technical direction
The microelectronics design industry has a design line width has been changed from 0.25 μm to 0.18 μm, and is working hard to work hard to 0.13 μm and 90 nm. After the target of 0.13 μm, 90% of the signal delay will be generated by the line interconnection. In order to design a high-performance circuit with nearly 2GHz, it is necessary to solve the problem of inductive, electric migration and substrate noise (and also have a problem of design complexity). What are the challenges faced in the next few years? How does standard organization face? When the design line width is reduced to 0.13μm or even more, there will be four main trends:
◇ Design and reuse; ◇ Design verification (including hardware and software); ◇ Interconnect issues will determine the requirements for time, power and noise; ◇ system-level chip design requirements.
Meeting the designer needs of future designers will be a model for many suppliers to provide solutions because the problem involved is too large and is too complicated, no company or entity can be independently resolved. In fact, people have a complete reason to believe that the role of basic research activities and independent industries will be equally important for the contribution of next-generation design problem solutions.
Later, the EDA will work in the following three aspects.
1 interoperability standard. The basis of all solutions is the components - interoperability standards for design tool development processes. We know that the EDA industry uses the standards required for industrial, regardless of who is formulated. However, the rapid development of today's market is turning advantage to those who can provide rapid adaptation and technology-leading organizations when providing standards. The leading company is investing in this regard, and companies that do not participate in the development of these standards must be borne alone. 2 Extend its advanced library format (ALF) standard, making it information in the physical field, and is the EDA developer can commit to solve the interconnected algorithm, so that the circuit designer is no longer subject to this problem when the circuit designer is no longer subject to this problem. Plast. 3 Develop new system-level design language standards. Standardization system chips design tools and languages make SOC truly reached the tide of the third microelectronics design revolution.
5 Strategic choice for domestic development
Since the current IT industry is not booming, and the EDA has increasing the trend of consolidation adjustments. Synopsys combined with avant! And Co-Design, Cadence combined with GDA, forming a few big giants. And each programmable device manufacturer, like Xilinx and Altera, also positively cooperate closely with EDA, so we must seize this timing and stronger development; otherwise, we must face the unfavorable situation in the future of life and monopoly giants.
In response to the development of the current hardware description language and the development strategy of national chip manufacturing and production, how to develop in the field of the original EDA foundation, making EDAs a reasonable, healthy and essential industries; the basic research activities and independent industries A reasonable combination of role, it is recommended to carry out the following work:
1 In order to achieve the autonomy of China's chip design, it must be consolidated. On the basis of combined with VHDL, promote the Verilog HDL design language, so that the bottom layer unit library of hardware design can be developed independently; 2 According to the current development trend of the current chip system, the system level The language is comparative study, making a choice in the language such as SuoerLog, Systemc, and the promotion of related tools, and cooperation with related enterprises, etc .; 3 deep into the comprehensive and simulation of HDL language, and strive to cooperate with foreign countries. On the basis of the establishment of EDA companies from the primary intellectual property rights; 4 Actively join EDA's current standardization work, understand, learn, apply, absorb, participate in and heavy; 5 Government actively joined, emphasis, study, study, research cooperation, and carry out Actually effective development model.
