I. Emphasize the need to write the style of Verilog code. Emphasizing that Verilog code is written, often a very popular topic, but it is very necessary. Each code writer has its own writing habits, and I like to write code according to my own habits. Write the code with yourself, read it is easy to accept and understand. Instead, you have more differences in code, reading and accepting some code, reading and accepting some. The programming master summed up, an excellent programmer, the length of the code can maintain approximately 10,000 lines. The degree of tidy code is largely affected by the maintenance difficulty of code. Follow the code written by code to write code, easy to read, understand, maintain, modify, track debugging, and organize documents. Instead, the code is written in the style, usually obscure, messy, will bring difficulties to the developer himself, modification work, will also bring a lot of trouble to the partners. (In fact, English Coding Style has another layer of meaning, more than a circuit, using that form of language description to describe the circuit more accurate, the circuit generated after synthesis is more reasonable. This article is more important Yes, write habits when writing Verilog code.) Second. Emphasize the purpose of writing specifications. The reduced space improves the tidy to track, analyze, and commission enhanced readability, help readers understand that the document is easy to exchange cooperation. Variables and signal naming specifications. 1. Name the system level signal. The system-level signal refers to the reset signal, set signal, clock signal, and the like need to be delivered to the global signal of each module; the system signal begins with a string SYS. 2. Low levels and letters N after a high-level signal. Such as: sysrst_n; fifofull_n; 3. After latching the latch, after adding the scribe and the letter R, the signal difference from the latch. Such as CPURAMRD signals, should be named cpuramrd_r after the latch is latched. After the low level effective signal is latched by the latch, its naming should be plus R after _n. If the cpuramrd_n signal, it should be named CPuramrd_nr multistage latched signal after the latch, which can be marked. Such as the CPURAMRD signal, after the two-stage trigger is latched, it should be named cpuramrd_rr. 4. Naming of the module. At the system design phase, you should be named for each module. The named method is to combine the individual words of the module English name to form an abbreviation between 3 to 5 characters. If the English name of the module has only one word, the top 3 letters of the word can be taken. Names of each module are suitable in 3 letters. For example: ARITHMATIC Logical Unit module, named Alu. Data Memory Interface module, named DMI. Decoder module named DEC. 5. Naming of interface signals between modules. All variables are divided into two parts, the first part indicates the data direction, where the data is sent before, the data receiver is behind, the second part is the data name. The two parts are separated by underline. The first part is all uppercase, and the second part all the first alphabet of all spelling or abbreviated English names, the remainder is lowercase. Example: CPUMMU_WRREQ, the upper left side is the first part, and the data direction is to the memory management unit module (MMU) from the CPU module. The loop right WR is the abbreviation of Write, and the REQ is the abbreviation of the request. The first letter of two abbreviations is capitalized, which is convenient for understanding. The entire variable means that the CPU is sent to the write request signal of the MMU. The naming of the module upper and lower hierarchy is also followed. If a signal passes from a module to multiple modules, its naming the main path of the response signal.
6. Module internal signal: The signal inside the module is connected by several words, and the abbreviation requirements can basically indicate the meaning of this word; words except for commonly used abbreviation methods (such as: Clock-> CLK, Write-> WR, Read- > RD, etc.), one of the first few letters (such as Frequency-> Freq, Variable-> var, etc.); the first letter of each abbreviated word; if you encounter two uppercase letters adjacent, middle Add a next line (such as Divn_CNTR); for example: sdramwren_n; flashhaddrlatchen; 4. Coding format specification. 1. Plus, add 1 to multiplexes between sections. If each always, the Initial statement is a section. Each section substantially completes a specific function, ie, is used to describe the generation of a few signals. A few rows of comments are described in each section to describe the section code, at least listed at least the meaning of the signals described in this section. 2. Do not use spaces to align, but use the Tab key, the width of the Tab key is set to 4 characters width. Do not have extra spaces at the end. 3. Comment. The annotation line to use // is ended in a semicolon; the annotation of / * / * / each occupies, and the head; example: // Edge Detector Used to synchronize the input signal; 4. Space Use: Different variables, and variables and symbols, a space should be retained between the variables and parentheses. A space should be retained between the Verilog keyword and any other string. Such as: always @ (...) When using braces and parentheses, there is a space in front of the front and post-brackets. Logical operators, arithmetic operators, comparison operators, etc., each of the other sides of the operator, separated from the variable; single operation count operator exception, directly in the operand, no spaces. Using //, there should be a space after //; do not have extra spaces at the end of the notes. Example: Assign Sramaddrbus = {Addrbus [31:24], Addrbus [7: 0]}; assign Divcntr [3: 0] = Divcntr [3: 0] 4'b0001; Assign Result = ~ OPERAND; 5. Same All statements of the level are aligned; initial, always and other statement blocks of Begin keywords follow the end of the Bank, the corresponding end keywords are aligned with initial, Always alignment; this is the benefit of this is to avoid the number of lines due to Begin exclusive Multiple; example: always @ (posedge sysclk or negedge sysrst) beginif (! Sysrst) DataOut <= 4'b0000; Else if (lden) begindataout <= datain; endelse data <= Data 4'b0001; end6. Different levels The statement is used to indent using the Tab key, and each layer is indented into a Tab; 8. In EndModule, EndTask, Endcase, etc., the keyword, etc., the keyword, the end of the code block, the name of this code block, the name of this code block; 9 The TSK is added before the TASK name to mark it. The FUNC is added before the name of the Function is marked.
