The basic structure of the VHDL syntax is like this:
User definition area
Entity definition area
Architecture definition district
User definition district is defined some standard libraries, and the Entity definition area is a definition of the appearance of the entity. The specifications of the I / O interface, the Architecture definition area is the internal function of the circuit describing the circuit, indicating what this circuit is used.
Ok, now start talking about the most simple example, similar to the software language hello, world, huh
Library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------
Entity aa IS
Port
PIN48: IN STD_LOGIC;
PIN20: OUT STD_LOGIC
);
End aa;
--------------------------------
Architecture BB of Aa IS
Begin
PIN20 <= PIN48;
END BB;
- It is similar to C // for comments, this way of writing is clear, nothing else, first of all library IEEE; define the standard IEEE library.
Then look at useieee.std_logic_1164.all; is all definitions of useiee.std_logic_1164 in the IEEE library
Similarly, use IEEE.STD_LOGIC_UNSIGNED.ALL; is all definitions in the Use IEEE.STD_LOGIC_UNSIGNED library
Now let's see the entity, Entity is the meaning of entities, and Entity's format is like this:
Entity Entity Name IS
Port
Pin Name: Enter the output status type;
Pin Name: Input Output Status Type
);
End entity name, so AA is the name of this entity, and PIN48 and PIN20 are the name of the pin. The representative is an input state. The OUT representative is the output state, and the STD_Logic representative is standard.
Logical type, there are other types, which will be described later.
Then we look at the structure:
Architecture BB of Aa IS
Begin
PIN20 <= PIN48;
END BB;
Architecture is the keyword of the structure. The BB is the name of the structure. Architecture BB refers to the name of BB is the structure of the structure. Architecture BB of AA refers to the structural BB of the AA entity, and IS representative is specified.
Begin
PIN20 <= PIN48;
END BB;
Here is the structural function of the structure, similar to the PASCAL syntax, PIN20 <= PIN48, the content of the pin PIN48 is transmitted to the PIN20 output. The input pin PIN48 is introduced to the output pin PIN20, similar to the assignment of the C language.
Question: Port
PIN48: IN STD_LOGIC;
PIN20: OUT STD_LOGIC
);
What is the PIN20: OUT STD_LOGIC statement?
A: The format is so, the last statement is not ';'
