HDL Profile Hardware Description Language HDL Design Circuit Method (Overview) In this chapter, I intend to introduce the following contents · Classical approach to the circuit design · Method for Applying EDA design circuit · Steps for HDL design circuit · HDL historical development and classification
Before everything starts, I want to mention a question first - what is our design? · The ultimate goal of integrated circuit design - the design of the chip integrated circuit design is to design silicon integrated circuits. The purpose of all processes is to make the communication wires that implement a certain functional electronic component and the connecting wires between the devices are fabricated on a small area of silicon wafers. Therefore, we have to be clear at the beginning of the concept, the ultimate goal of IC (integrated circuit) is to go to the optical mask version of the optical mask version of the chip, which is the layout of mass production chips. It is the ultimate in the event of various functions of integrated circuits. Mask drawings are related to specific production lines and production processes, as the same machine code will change because of the specific machine type. Therefore, even if the product is exactly the same, the chip may correspond to a variety of different mask layout. For example, 1u's layout, 2U's layout, or layout of 1U production line A, 1U production line B layout - these four layouts are basically no repetition. Even if you am zoomed or narrowing, the layout of 1U and 2U process is definitely not the correspondence of this simple geometric size X2. · Maintainable document for integrated circuit design
In fact, we use HDL to design the circuit design, which may not be a complete integrated circuit design. Similar to the difference between the assembly language and the machine code, our daily IC design is usually HDL-independent of the actual production process, and we pay attention to a series of products that can be maintained. In this regard, computers are the same. We may have to retain source code, after compiling files (circuit schematic), but will not deliberately retain those corresponding assembly instructions (logic gate circuits), and will never track or try to save machine code (mask map) . Within the living life of an actual electronic circuit, we often need to modify, enhance or improve its functions. Reliability, portability, maintainability, etc., those that have nothing to do, therefore become our needs. We are essentially less likely to keep the final mask version of the paper unless the circuit design is made. Within the scope of our discussion, we will only keep HDL code, and the gate-class circuit diagram, because these are readable and have nothing to do with specific production processes. The layout seen on the production may be partially put in the design. This is not caused by the horses and tiger of the designer, usually for the necessary modifications for the reliability of the product. These contents involve semiconductor knowledge in the field of microelectronics, parasitic and delayed effects under high frequency and deep microscopic conditions, are not discussed here.
(1) Progress in circuit design 1.1 Electronic circuit traditional design concept Traditional digital electronic circuit design, can be said that development time is an index function of design functions. The integrated circuit of the analog signal is complex and cannot be generalized, but the function of the digital circuit can be expressed in an exception to represent the logic function and register. The logic map of the function is logically minimized design. If necessary, it will be converted to a specific door (for example, unified as a non-door, or non-door) specification. Pat together according to existing devices, then mix each module. This mainly causes the following questions that these issues have been fundamentally solved in EDA assistance design: (*) requires a unified component. The micro-mold circuit multi-case cascades N logical features chip and register chip. Instead of adopting a special chip; the small industrial circuit is not unreliable to use a multi-purpose such as C51, programmable control chips. The utilization efficiency of the chip is not high, the scale cannot be done, and the ability to perform in frequency is limited, and most circuits are only suitable for small batch production. (1) Simulation and commissioning in the traditional hardware design method, simulation and commissioning can only be performed after the system hardware design in the traditional hardware design method. Since the instrument for simulation and debugging is generally a system emulator, a logic analyzer, an oscilloscope, and the like. Therefore, simulation and debugging can only be made after the hardware system is physically composed. The problem of system design is only available in later periods. This has a considerable requirement for the designer. One, considering that there is no mistake, the system design has a little error, then it may lead to redesign the system, which makes the system design cycle increase. (2) The main design document is the electromechanical graph. This is for the ASIC (Appication Specified IC) design of the self-developing chip. After designing and adjusting the system with a traditional hardware design method, the hardware design file formed will be a number of design electrical schematic. I believe the name and interconnect relationship of the brother logic element in the electrical graph, which is the basis for the user's use and maintenance system. For small systems, this paper takes tens to hundreds of hundreds. But the large system drawing may be a few thousand or hundreds of thousands. This paper is a dramatic difficulty for users or researchers. 1.2 Revolutionary Breakthrough of Electronic Circuit Design Method · The digital circuit design of comprehensive tools has been developed rapidly, and the complexity of circuit has grown in the legendary geometric speed. People grow the functional demand, is already enough to understand that the use of logic map design Boolean functions is very laborious or even. The designer must manually design the door network to minimize the door level. Later, people developed the software of the Boolean function to automatically convert the Boolean function to a specific door (with non-, different or door). Successfully solved the low efficiency of high cost. The functional processes completed by these software are now often speaking logic synthesis. The birth of this type of software marks the beginning of the EDA auxiliary design electronic circuitry. Logical integrated features: Convert Boolean function to the door and minimize. · The age of integrated end Ni HDL, the design software does not design hardware; design hardware does not contact software. For those professional arrivals, specifically tell the actual content of this integrated, it is more comparable to the hair; talking about these comprehensive practical content, I am really looking for a bald. But I believe that many people in this era have a computer language, and these only need some integration. This logical integrated function is like compiled compilation, circuit design requires other synthesis, and it is specifically introduced when the principle is involved. The intelligence of logical intelligence is only considerable to call functions in the language, generates .Obj files (intermediate steps for Basic's Compile); because the entire circuit design requires other comprehensive processes, logical integrated works The degree is actually lower than compilation of computer programming tools. Various EDA design software has been admitted, gradually completing the various simulations and comprehensive functions required for HDL-> layout.
Among them, there is a representative of the 90s popular IT Candence Orcad and MaxPlus II. · Abstract Introduction HDL Development Software Use it, it is to complete the integrated tool. Comprehensive HDL code, equivalent to the advanced language code of the computer language. The results after synthesis, although the next step is still needed, but it has been further close to the physics of the chip. This is wearing an important engineering complexity concept - abstract. The so-called language abstraction is to describe the complex things in language without describing the details inside the matter. Functions, the process is the main means of processing complexity in the language. Abstractions greatly reduce the complexity of the entire system, more levels, making it easier for designers to understand. The Basic / C language of the computer's advanced language is closer to the human language, and its content is more than the call function, the control process, and the like. There is no doubt that for the computer, the computer's advanced language is more .EXE /.com file more 'abstract', the computer needs 'understand' (multi-step integrated / computer programming compiled in HDL) can be executed. In response to the HDL design circuit, the HDL code is required to be put into production after 3 synthesis. Each synthesis reduces the degree of abstraction of HDL code, it is more close to the actual production; at the same time, the drawings of people are even more large, and the information seen is more exact and specific. (2) Using the HDL and Advanced Integrated Tool Design Circuit Design (Preliminary Concept) Development from the electronic circuit to today, the number of transistors contained in each chip grows almost in accordance with the geometric speed of the index. For VLSI silicon wafers that may contain millions of millions of MOS transistors, the old set of old sets is tantamount to the sea water. Who will use ASM to write an image-based interactive multimedia game? Write advanced computer programs, which is probably aware of hardware than engaging hardware. But in order to illustrate the related content of hardware design, I hereby talked about the process of programming: writing advanced language code, generating executable files, and verifying whether to verify the function of our design by running this program, is it because Consider the bug generated in the no week. Under determination, the reliability of the test program is determined to complete the specified function. Finally, optimize the code, and improve the efficiency of the program execution as much as possible. These steps are required during HDL design VLSI. In the past, design methods need to be given the process of test production, and then the equipment is applied to the input and outputs. With the help of EDA, we can use software to simulate test. · The flow of integrated circuit automation 3 behavior / high-level description - [behavioral integrated] -> logic function - [logic synthesis] -> 2 gate description "- [layout and wiring] -> Physics Comprehensive] -> The mask graphics have a boundary point of 1 generation circuit CAD and 2 generation circuit CAD in content. But from macro, they can only consist of one step in synthesis, and do not constitute parallel relationships with other descriptions and synthesis. · Three descriptions and three synthesis of three synthesis, in fact, the description of the mathematical model of the entire system. In general, a description of the behavior level of the system is a problem with the presence of the math model in the design of the design of the system behavior. This stage design is designed to detect whether the structure and work processes have reached the design requirements. (1) High-level comprehensive / behavioral synthesis: The function of the system, the functions of each component, and its input output, and then the synthesis. At the same time, verification is performed by high-level hardware simulation. RTL Description (2) Logic Synthesis. Convert logic grade behavior into a gate-level description (the structure description of the gate level is called a network table description). At this time, if necessary, the logical results can also be output as the schematic mode (requires software support). In other words, the logical synthesis is equivalent to the logic electrical map of the system in accordance with the requirements of the system according to the requirements of the system (completed the compilation task, generated .exe file). At the same time, you have to do a gate-class logic simulation and test synthesis.
Thereafter, simulate the logic integrated results on the gate-level circuit and check the timing relationship between them. If everything is normal, the system's hardware design work is basically over; if there is a problem with the problem, it will return to the previous level to find and modify the corresponding error, and continue unfinished work. If we have completed logical synthesis, complete regular hardware design, we have two options to create hardware that implements this function. The first is to use the automatic wiring tool to convert the menu to the corresponding ASIC production process (or artificial participation), making the mask layout on the production line to make an ASCI chip. The other is to write the program to the FPGA (field programmable gate array), implement its function with FPGA or CPLD, etc. Programmable devices. (3 *) Physical synthesis. (If the purpose of the circuit design is to utilize the programmable device implementation, this step will not be necessary). Conversion of the menu description into a layout, that is, the design of the layout. This type of connection relationship is determined for each unit, the size, the position, and the internal connection relationship. This label marks the 3 different stages of the EDA. 1 is the prototype stage of computer-aided design in the 1970s. At this stage, the circuit design is basically organically involved, and the computer is only a computer platform and drawing tool. If it has intelligence, it means that it has geometric geometric verification based on geometric graphics. Designers get rid of the method of complicating, and wrongful manual design layouts, greatly improving efficiency. But the good is not long, these CADs can only adapt to early design needs. In large-scale circuits, it still does not shorten the design cycle. Although most errors generated by it are errors in personnel, its non-intelligent disadvantages will appear immediately with the development speed of the circuit scale. 2 is the true opening of the auxiliary design, providing some intelligent functions. Provide logic graph input, logical simulation, test code generation, circuit simulation, circuit simulation, layout design, vernometry, etc. He not only has a full-custom circuit's layout editing tool, more gate array, and automatic layout tool for the standard unit circuit. Consistency check, the layout parameter extraction can also be automatically implemented by CAD. This CAD was known as CAE (Computer-aided Engineering). These functions have largely guaranteed reliability, and the beauty is not enough. The actual production needs to simulate. The second generation CAD still cannot simulate. 3 is the stage of advanced design automation in the 1990s. At all stages of all circuit design can be done by means of computer intelligence. We have been able to design the circuit through a circuit description approaching the human natural language. The sign of this stage is the birth of HDL automation design tools. · From the top-down design concept, the early classic design method, because it starts from the underlying device to start designing circuits, often referred to as a Bottom UP method. The corresponding Chinese name is from bottom to design. The method of the EDA design circuit, the macro sequence is basically the opposite, referred to as top-down design method - Top Down design method. The so-called so-down design method is from the overall functional requirements of the system, and the top-down step-by-step design content is refined, and finally the hardware overall and concrete design. In the hardware design method using HDL, designers are based on abstract different levels, from top (most abstract), down (most specific) hardware. When doing Top-down is designing,
· Specific, from the top, design electronic circuit's forward design process: behavioral design -> Structural design -> Logic Design -> Circuit Design -> Mage Design The corresponding bottom Up is designed, Top-down method in the design of the actual large-scale circuit: system division, decomposition -> unit design -> function block design -> Subsystem design -> system assembly
Why is it a forward design? Because there is a reverse design. The reverse design is from functional to circuit, gradually designing the design method of demand; with this, there is also a method of analyzing from circuitry to function. If the analysis is modified, it constitutes a reverse design. Reverse Design (Top Down) Process: Version Analysis (Analyzing Out of Mask Edition) -> Circuit Drawings (Analysis Logic Circuit) -> Functional Analysis -> Structure Modification -> Logic Design -> Circuit Design -> Mage Design Reverse Design (Bottom UP) Flow Version Analysis -> Circuit Drawing -> Function Analysis -> Unit Design -> Function Block Design -> Subsystem Design -> System Design Here is the content involved in our reverse design. First, we don't do reverse design. An industrial method of extracting circuits from the chip in reverse design. This method is still almost impossible in VLSI or ULSI as the mainstream electronic circuit design. In 1997, there were nearly 4 billion transistors on a industrial advanced CHIP. The analysis mask version not only requires the relationship between the black box test input and output, but also uses the X-bit perspective, the electron beam measurement (later MOCCII, and the difficulty of reverse engineering). X-ray is because of the wavelength of IC, because the diffraction effect is basically blind; because the radi penetration ability is proportional to the length of the wavelength, the shorter wavelength rays are even more Not. The MOS circuit is a voltage control circuit, and it can work under high frequencies, which has been widely used in the modern digital circuit IC field. The current of the electron beam, the analysis method of the voltage measurement chip, and the number of layers of the chip is increasing, and the frequency is increasingly difficult. High manpower, the investment of material resources also takes a few years to analyze it. In the 1990s, Israel exported to China's electronic reconnaissance warning machine without radar, and did the country's national strength was then then then there were so dock.
Second, our design method is generally not a single Top-Down or Bottom-Up. After we are familiar with the macro structure and function of a system, it is often used to use a macro Bottom-Up, microscopically top-down. First, you need to perform behavioral design, to determine the function, performance, and size and cost of the chip allowed by the VLSI chip. Then make the structural design, according to the characteristics of the chip, the decomposition is clear, the interrelated subsystem, which is clear, as simple as possible, as simple as possible, to obtain a unified presidential structure. These structures may include arithmetic operation units, control units, data channels, various algorithm state, and the like.
Examples are exemplified now. The design of the CPU can be counted as a big project, we know that it is divided into registers, controllers, and operators, and we are definitely impossible to synchronize such a large system. First, it is divided into several small systems according to the function, and then determine those subsystems between them need to pass data. When we clarify the CPU parallel computing capacity, the internal data lines and control signal lines of the data transfer are set to the internal channel. Then we designed each device separately, and then connect these devices to our approach to the way, constitute our entire system-CPU. But we absolutely do not design such a clear function, the structure can be clear subsystem. When designing the CPU subsystem, you will use top-down to design. We describe its features and interfaces, describe its logic, and then automatically generate its logic diagrams with HDL, circuit diagram.
Half a day, what is the relationship between HDL, HDL programming, is there any relationship with computer traditional programming languages? Before I really start contacting the exciting VHDL programming, I plan to come to HDL to develop history and classification.
The first chapter of the Language Basis of VHDL - Nativity, Development and Category Before everything, I would like to explain some of our regularities. VHDL, Type High Speed Integrated Circuit Hardware Description Language, Ultra High Speed Integrated Circuit Hardware Description Language. 1.HDLHDL, Hardware Description Language, is a language for electronic system hardware behavior description, structural description, data stream description. As the research is in-depth, the simulation of electronic system design or hybrid electronic system design is now exploited. Designing electronic systems with HDL has 2 reasonsive reasons: shorten design time, simplify everyday maintenance.
From the description method, HDL has two -GHDL (Graphic Hardware Description Language) and Word HardWare Description Language. GHDL is intuitive and clear, in logic circuit diagram, the electronic design of the status flow chart is a classic method; of course, GHDL is also very old. With the development of the computer language, the text description language (WHDL) has been able to completely replace GHDL. Although WHDL and GHDL are mixed in the actual digital electronic design system, HDL is generally generally referring to WHDL.
HDL so-called "classification" has always been a headache. There are a wide variety of HDL languages, and there is 100 kinds of vitality that is still in use. Higher colleges, research units, and EDA have their own HDL language. Some are corporate standards, some are IEEE standards. As we all know, market share determines its standardization promotion, so-called standards follow public usage. The current software and hardware market share determines that we will usually have access to these two: vHDL languages, Verilog HDL language. These two languages have become an IEEE standard language.
This doesn't mean that other HDL is not common, nor does it say that other HDLs cannot be self-contained, and then continue to classify. Representative common languages in the remaining HDL language include Abel, AHDL, hardware C language, which completely forms its own unique language style, which is generally used in considerable series of products. Due to the AHDL language, the company has a wide range of users in many universities in many universities. It can be said that the proportion of people in the AHDL language for hardware design is high, and the impact of considerable regions and the degree of popularity even exceed VHDL and Verlog.
Although there are many types, although grammar, style, and standards are different, if it appears from its predecessor, people are unlavable to divide HDL into 2 categories: Pascal style and C style. Said here, people can naturally think of these two language style. Pascal named by French mathematician, Physiologist Pasca, its language is quite strictly prohibited, and language is naturally readable. The world's most creative place in the world in the 1960s - Bel laboratory manufactured, completely represents the style of opening the sky, gathers strong free consciousness and creativity. VHDL belongs to the Pascal style, Verlog represents a C style.
These styles have different requirements for HDL in teaching, and different degrees of students will feel different; from another perspective, it is inevitable to affect scholars' choices. The earliest and grammar of VHDL, and Verilog HDL is a hardware description language developed on the C language, and the syntax is more free. Compared to VHDL and Verilog HDL, VHDL's writing rules are tissue than Verilog, but Verilog's free syntax is easy to make a few beginners mistakes. Foreign electronic majors will professor VHDL in the undergraduate phase, professor Verilog in the graduate stage. From the domestic perspective, VHDL's reference book is much easier to find information, and Verilog HDL's reference book is relatively small, which brings some difficulties to study Verilog HDL. Common HDL profile
VHDL VHDL is actually a standard language generated by the requirements of the US Department of Defense Electronic System. At that time, the US officially entrusted many projects to contractors, and then did the project's summary. But because the contractor has a different set of standards, the information exchange and maintenance are more difficult. In order to reduce R & D fees, the US government has avoided full design, which has prompted the Ministry of National Defense to be equally unified to all contractors - unified HDL language. Strong function, strict grammar, VHDL having good readability is like this. The Government led the VHDL R & D team established in June 81 and proposed an industrial standard HDL. IBM, TI, Intermetrics, R & D Language Versions and Development Software Environments have been added in the third quarter of 83. In the 86th IEEE Standardization, the IEEE Standardization Organization has begun to discuss the VHDL language standard for a year. In December 87, I passed standard review, namely STD 1076-1987.
Verilogcandence is a well-known EDA company. The company's Verilog HDL was created by the Phil Moorby of Gate Way Design Automatic in 1983. His successfully designed Verilog-XL emulator in '84 - '85, raised the fast-door XL algorithm in 86, making the Verilog HDL language more abundant and evening, got the favor of EDA design companies. In 89, Candence acquired the GDA in Moorby, from this Verlog HDL, which became the private property of CANDENCE. Become a hardware description language in CANDENCE in the EDA design environment. After the unremitting efforts of Candence, Verilog HDL became an IEEE standard in 95 and is the first HDL language standard of civil companies, namely Verilog HDL 1364-1995. Since its HDL is based on C, it has enabled C language based designers to get started faster.
First, June 07, 2004 11:42 AM
