Use the Make program to create a line of pipeline for large projects: Javaaresearch.org-abel_cao
2/7/2003
URL:
Http://www.zdnet.com.cn/developer/code/story/0,3800066897,39143422,00.htm
If you rely on batch files or scripts to compile code, and projects are getting bigger with the increase in the number of established, you might use the Make program. The Make program can take a line processing for the establishment of large projects and only recompiles the changed file.
Also, if you rely on the IDE development tool to generate a code, the Make program is hidden in the development tool. Understand it allows you to better control the establishment process.
The Make program is known to be known, in fact, for very large items. Don't be afraid, in fact, he didn't think so complicated.
From simple start
The basic operation of the make program is very simple: make programs read text files typically called Makefile, which contains a range of rules that use commands to generate target programs. Below is the generality of a rule in Makefile:
Target: Dependents Commands
Targets is the file generated by the establishment process - for example, the final executable binary code generated by the connector or an intermediate target file generated by the compiler and assembly language interpreter. Dependents refers to the files required to establish a goal. For example, all target files or header files depending on the target file depending on the binary code can be executed. Commands refers to the instructions or programs that claim to be a target.
Here is a very simple example (using the Microsoft C Compiler tool). This makefile means generating an executable file from a single aid. Note that the final executable program is the first target in makefile.
Main.exe: main.obj link /out:main.exe main.objmain.obj: main.c cl -c main.c
When Make runtime, it analyzes all goals and the relationship of the dependencies, checks the difference in file timestamp, and executes the minimum command set required to generate the final executor.
Add some files
Add some files
If you add more files in your project, you can extend your Makefile. Below is a Makefile joined more source files:
Main.exe: main.obj file.obj test.obj link /out:Obj.exe main.obj file.obj test.objmain.obj: main.c file.h test.h cl -c main.cfile.obj: File.c file.h cl -c file.ctest.obj: Test.c test.h cl-co test.c
In this makefile, the header file has also dependent on the file. So, main.obj is to generate from main.c, file.h or test.h. .
This is enough for a lot of projects. But if you are more ambitious or make a large Makefiles easy to maintain, you need more skill.
Use variables
Variables are very useful for storing repeatable text (eg, fixed path name, file list, tool name and command line flag), you can easily change him in one place. Use the following rules to use variables:
$ (Variable)
Use implicit rules
Implicit rules allow you to define a general formula for generating target files from different dependencies. A implicit command is only executed when there is no clear command. This simplifies your makefile and avoids the same commands to be repeated.
Below is an implicit rule that generates an OBJ file from a C file:
.c.Obj: Cl-C $ <$ Makefile can have a lot of implicit rules. For example, you can increase implicit rules to describe how to generate target files from assembly code. Below is a complicated Makefile with implicit rules and variables: # Variablescc = CLCFLAGS = -cobj = main.obj file.obj Test.obj # Implicit Rules.c.Obj: $ (cc) $ (cflags) $ @ # explicit rulesmain.exe: $ (b) link / out: $ @ $ (Obj) main.obj: main.c file.h test.hfile.obj: file.c file.htest.obj: Test.c test.h For some Make programs, you may need to increase the following line in the enlightenment of Makefile .Suffixes: .c .obj .h These basic Makefile tools need you to study at a point, they are valid for most Make programs. Once you have the characteristics, you can have a long time when you create a large project.
