6.6 UART0P87C51MX2 has two enhanced serial ports, and there is a separate baud rate generator, they are and 8x51r series
Serial port remains compatible with this baud rate generator, the first serial port (UART0) can select Timer1 overflow or
Timer2 overflow or a separate baud rate generator, serial port 1 (UART1) selects the baud rate generator to produce
Birth rate, in addition to the baud rate generator, more than the standard 80C51 including structural error detection, automatic identification address
You can choose a dual cache and some interrupt selection, which two serial ports can be selected for the port specified. Each port can have four operating modes 6.6.1 mode 0 Continuous data into or exit by RXD_N, TXD_N output shift clock signal, only 8 bits transmission or receiving data
LSB is preferred. The baud rate is fixed to 1 / 6CPU clock frequency, send or receive byte data via RXD, using TXD legs
Output synchronous clock signals. 6.6.2 Mode 1 Transferring 10-bit data via the TXD foot to receive 10-bit data content through the RXD foot, and start the bit 0,8 bit data bit stop
Bit 1, stop bits in the S0CON / S1CON special register when performing data reception RB8_0 / RB8_1, UART0
The baud rate is variable and determined by the clock overflow rate and the baud rate generator. 6.2.3 Mode 211-bit TXD foot transfer, RXD pin is received, start bit 0, 8-bit data bit, a programmable 9th, one stop
Stop. When data transmission is performed, the 9th bit [SNCON TB8_N] can be adjusted to 0 [to give an example as the parity school.
In the inspection of TB8_N], when the data is received, the 9th bit is stored in S0CON / S1CON from RB8_N, and stopping the bits will be ignored.
For serial port 0, the baud rate is a CPU clock frequency programmable to 1/16 or 1/32, by pair PCO
The SMOD1 in n is set. For serial port 1, the baud rate is derived from the baud rate generator. 6.6.4 Mode 31-bit TXD foot transfer, RXD pin for receiving, start bit 0, 8 bit data bit, a programmable 9th, one stop
Bit. In fact, the relationship between pattern three and mode 2 is except for baud rates. For serial port 0, the baud rate of mode 3
The overflow rate (T2CON.5-4) and baud rate generator at TIME1 / 2. For serial port 1 baud rate generator is wave
The unique source produced by the special rate. In the four working modes, S0BUF / S1BUF will be used as a target through any instructions.
The register is used. Mode 0 requires 2 conditions Ri0 / Ri1 = 0 and ren_0 / ren when receiving the initial
_1 = 1, other modes only need REN_0 / REN_1 = 1. 6.6.5 Special registers and external special register space General UART0 and control bits are in a normal register. However, external control and UART1 registers expand external special register space in MX. Register Description SFR Location MX Extended SFR Location PCON Power Control 87H T2CON Timer2 Control C8H S0CON Serial Port 0 Control 98H S0BUF Serial Port 0 Data Buffer 99H S0ADDR Serial Port 0 Address A9H S0ADEN Serial Port 0 Address Enable B9H S0STAT Serial Port 0 Status 8CH S1CON Serial Port 1 Control 80H S1BUF Serial Port 1 Data Buffer 81H S1ADDR Serial Port 1 Address 82H S1ADEN Serial Port 1 Address Enable 83H S1STAT Serial Port 1 Status 84H BRGR1 Baud Rate Generator Rate High Byte 87H BRGR0 Baud Rate Generator Rate Low Byte 86H BRGCON Baud Rate Generator Control 85H Table 146.6.6 Port Botte Rate Generator and Select P87C51MX2 Enhanced Serial Port There is an associated baud rate generator, p87c51mx2 microphes
The baud rate generator in the robot family is an easy to get a better handling of baud rate than the standard clock source.
Preparation. The baud rate and the baud rate handle special registers BRGR1, BRGR2 to control. BRGR1.7-0,
BRGR2.7-0 is 16-bit as a division, providing the same way of working with Timer1 / 2, such as
The voter rate generator has been used, and Timer1 / 2 can be used as another clock function. UART0 uses Timer1 / 2 or baud rate generator to output, but UART1 can only be used as
Baud rate generator. Note In UART0, Timer1 will be divided into 2, and if the SMOD1 bit PCON.7 is cleared, the Timer2 and the stand-alone baud rate generator will not be split. Figure 42UART0 can use different baud rates to send and receive data, one of the clocks come from Timer
1 The other is from Timer2 or a separate baud rate generator. It is impossible to take Tim at the same time.
ER2 or baud rate generator provides a different time to UART0. See Table 15 and Figure 42 Table 15S0CON.7 (SM0_0) S0CON.6 (SM1_0) T2CON.5 / 4 (RCLK - Receive
Tclk - transmit) PCON.7 (SMOD1) BRGCON.1 (S0BRGS)
Receive / Transmit Baud Rate for UART 0 Number Of Data Bits in Transfer 0 0 x x fosc / 6 8 0 1 0 0 x T1_Rate / 32 * 8 0 1 x T1_Rate / 16 * 1 x 0 T2_RATE / 16 * 1 x 1 FOSC / (BRATE 16) * 1 0 x 0 x fosc / 32 8 1 1 0 x 1 x fosc / 16 1 0 0 x T1_RATE / 32 * 8 1 0 1 x T1_RATE / 16 * 1 x 0 T2_RATE / 16 * 1 x 1 FOSC / (Brate 16) * * Receiver and transmit clocks can be different. Table 16S1CON.7 (SM0_1) S1CON.6 (SM1_1) BAUD RATE for UART 1
Number of Data Bits in Transfer 0 0 FOSC / 6 8 0 1 FOSC / (Brate 16) * 8 1 0 FOSC / (BRATE 16) * 8 1 1 FOSC / (BRATE 16) * 8 1 * UART 1 HAS The Same Receive and Transmit Baud Rate. 6.6.7 Frame error frame error Fe_N is published by the status register; if SMOD0 (PCON.6) is 1, U
ART0, UART1 frame error makes S0CON.7, S1CON.7 each valid, here it is recommended to recommend SM0_1, and SM0_N is set before SMOD0 is set to 1. 6.6.8 Status Register All enhanced serial ports have a status register containing some control bits 1.DBMOD_N (n = 0, 1): The enhanced serial port has double buffer, in order to compatibility with existing 80C51 devices
Setting this bit is 0, then disabled using double buffer. 2.intl0_n: UART Allows an interrupt when starting or ending stop bits, this bit is set
For 0, the TX interrupt is selected. When the end bit starts to generate, pay attention to if it is a single buffer, if TX is stopped at the end
When the bit is interrupted, there will be some interval when transmitted next time. Mode 0 in the UART port
It must be cleared 0.3.CIDIS_N: UART causes TX / RX combined interrupt or separate TX or RX interrupts, set
Use a combination interrupt for 0. 4.Disel_n: This bit is used when dBMOD_N = 1, if dbmod_n = 0
This bit will be set to be compatible for later. These bit control double buffer is turned on the number of interrupts, if set to
0 The number of TX interrupts and the number of characters transmitted is the same. If it is 1, add an interrupt INTL0_N =
0 Start or INTL0_N = 1 Interrupt when the stop bit is ended. Finally, this interrupt flag data transmission operation ends
. 5.Stint_n (n = 0, 1): If it is 1 Fe_n, BR_N, OE_n can generate an interrupt shown in Figure 446.6.9 More about UART mode 1 Detection RXD pin starts from 1-0, RXD is a sample basis for 1/16's determined baud rate. When the hop is detected, the 16-bit counter will immediately re-adjust the number of new receiving positions. Ri = 0, or SM2 = 0 or accept stop bit when the bottom condition produces a shift pulse
1 At the time of SBUF or RB8 (RB8_0 for UART0, RB8_1 for Uart1), and set
Setting RI (Ri_0 for Uart0, Ri_1 for UART1) will happen. 6.6.10 More Mode 2 3 Receive mode of the UART is the same as the mode 1 of the UART. When the shift pulse is generated, the SM2 = 0 or the 9th bit is 1 is generated, and the SBUF or R is set.
B8 and set RI. If one of the conditions are not satisfied, accepting the village will be lost forever, and ri is not
Will be set. If all the conditions are satisfied, the 9th bit accepted will be stored in RB8, the first 8
The bit data is placed in the SBUF. 6.6.11 Examples of Data Transport in Different UART Modules Figures 45-47 show that the single-byte transmission process is not used in the mode 1 2 3, and the double buffer is activated. The serial port recently writes SNBUF data, and the current data is being transferred.
When the bit register. The advantage of double buffer applications is that only one end stop bit is transmitted at the time of transmission characters. In order to finish
When the 80C51 completes the stop bit of the previous character, you need to set the next character end bit, double
The buffer allows the next character to be loaded at any time before the end of the previous character stop bit transmission. Double buffer
DBMOD_N (SNSTAT.7) = 1 is activated, if the double buffer is turned off, then the P87C51 is fully compatible with the 80C51 serial port. 6.6.13 Double buffering transmission interrupts do not use dual buffer mode, the transmission interrupt can select the stop bit to start or end the interrupt. Interrupt
That is to let the program know that you can receive new characters, as a result, it is changed when the dual buffer is scheduled. When using a double buffer, the interrupt is generated when transmitted by the buffer register to the shift register, so if the shift is sent
The depot is in an idle state, then generating an interrupt will be transferred to the shift register for transmission.
lose. If the buffer is filling the data, the shift register is being sent, it is not finished, only waiting to send the word
The stop bit of the character starts or ends. Note that if the data supplements in the buffer register always completed before the previous shift register is stopped, then
No idle time does not appear during transmission. Also, if there is an interrupt if it happens at the end of the stop bit.
To carry out data in the buffer buffer. If DBISEL = 0 is then generated when the data is transmitted by the Buffer Register to the end of the shift register
An interrupt. This makes each character generate an interrupt if dbisel = 1 serial port is the same, as long as
The stop bit of the transmission register and the Buffer register are empty. 6.6.15 Multi-Processing Dialog UART Mode 2, 3 has special provisioning to multiprocessing dialogue, 9 data bits in this mode will be received
Or transfer, port interrupts are activated when RB8 = 1, this feature is set to SCON SM2_n
carry out. A multi-process dialogue using this feature, when the host wants to talk to some other slave dialogue,
First send an address of the target slave, one address byte is different from the data byte, and the 9th bit is 1 mark as the address byte.
The 0 mark is data byte. There is no way from the chance to interrupt the 9th bit of 0 frames, will not cause the slave interrupt reception.
. In any case, the host needs to set the 9th bit to 1 to make all the slave interrupts, allow the slave to receive data.
Detecting whether it is the address, the source of the base is clearly removed, and his SM2_N bit is cleared, ready to receive data, the slave will not go
Addressing until their SM2_N bit is set, then keep the processing. Ignore subsequent data. SM2_n does not work in mode 0 mode 1, used as the validity of the test stop bit, so for processing
There are many frames. When the UART receives SM2_N = 1 in the mode, the received interrupt does not function to know that a valid stop check bit is received. 6.7I2C serial I0I2C bus performs information transmission by two lines SCD, SDL and external devices. There are several features: 1. Bidirectional data transmission between the main bid 2. Multi-channel control without the control center 3. The transmission between multiple hosts requires arbitration to avoid bus data conflicts 4. The synchronization of the serial clock is passed through one The bus is transmitted in different bit rates 5. Synchronization of serial clocks can be used to make a handshake mechanism to hang or restore 6. The I2C bus can be used for diagnostics and detect typical I2C bus configurations as shown in Figure 50, The direction bit state, the I2C can carry out two ways of transmission 1. From the transmission of the host transmitter to the slave receiver, the host sends the first byte as the slave address, behind is
Data bytes, the slave sends a response bit according to each received by one byte 2. From the slave to the host data transmission mode, the first byte is transmitted from the host to respond from the host.
It is the slave to send data bytes from the host, and the host will return a response per segment. the last one
Bytes are special hosts that will not return. The host generates all serial clock start and stop bits,
At the end of the start condition to stop conditions or repeated transmission, since the repeated start transfer condition is the beginning of the next transmission
Therefore, the I2C bus is a one-byte-oriented I2C bus that does not be released by the device provided by the device that provides four operating modes: host transmission mode, main receiver mode,
From the receiver mode, from the transmitter mode. Interface interaction of the CPU and I2C bus through 6 special registers: I2CON (I2C Control Register) I2DAT (I2C Data)
Register) I2STAT (I2C Status Register) I2ADR (I2C Address Register) I2SCLH (I2C Duty Free)
) I2SCLL (low position of I2C duty factor) 6.7.1 I2C Data Register I2DAT register contains data content to be transmitted or received. The CPU can read and write this 8-digit register
This means that you can only visit this time when you don't have a shift process.
Deposits, I2DAT content remains complete as long as the SI bit is set. I2DAT transmission is often shifted from right to left, most
Starting is MSB (i2dat.7) to start transfer, one byte is transferred, keeping a bit of receiving returned in m
SB. I2DAT address: 93h i2dat.7 i2dat.6 i2dat.5 i2dat.4 i2dat.3
I2DAT.2 I2DAT.1 I2DAT.0 does not set a bit weight source: any reset resulting in reset value: 00000000B6.7.2 I2C slave address register I2ADR register is readable to be writable, only at the I2C bus is set to the slave Mode, in host mode, this register cannot afford
Role, the LSB bit in I2ADR is a full call, when this bit is set, the address (00h) is recognized i2ADR address: 94H i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2
I2ADR.1 i2adr.0 GC does not set up bitstocks: any reset resulting in reset weight: 00000000bi2adr starts from slave mode
The role does not work in the host mode GC: Full-call mode If set, you will identify the address 00h, otherwise 6.7.3 I2C control register CPU can read and write this register, two bits rely on hardware, Si bit is from hardware Set, the STO bit is clear by hardware
except. CRSEL determines that the frequency of SCL is in host mode, and the automatic synchronization clock frequency is 400kHz to I2C bus devices. When crsel = 1, I2C uses T1 overflow rate / 2 as an I2C clock ratio, T1 automatically loads 8-bit mode 2
under. I2C data magnification = timing overflow ratio / 2 = f (OSC) / (256-load value)) If the oscillator frequency is 12MHz, the content of the re-entry T1 is between 0-255, so the I2C data magnification is 5.86 -
Between 1500kbit / sec, pay attention to operation in 12MHz in the oscillating frequency, the I2C data magnification will not be 1 Mbit / Sec, because
For the minimum re-entry data 254, the data magnification is 750kbit / sec. When CRSEL = 0, the I2C internal clock generator is based on the I2SCL, I2SCH, and the duty ratio is unnecessary.
The STA bit is a start bit, setting this bit makes I2C enter the host mode, transmits a starting position or reply a re-
Start bit. STO is a stop sign, setting this bit, causes the I2C to send a stop condition or get a slave transmission
mistake. 6.7.4I2C status bit register This is a read-only register containing the I2C status information code, the smallest three bits are 0, with 26 state code, when code
When F8h, there is no relevant existing information and Si is not set, the other 25 codecs correspond to the defined I2C
Various states When other states, Si will be set, Table 18 and 21 have a detailed description. I2stat address: 92H STA.4 STA.3 STA.2 STA.1 STA.0 0
0 0 No source can be set: any reset causes the reset value: F8HI2STAT I2C status register three
Bit is always 06.7.5 I2C duty cycle register I2SCL I2SCH When the internal SCL generator is selected by setting CRSEL = 0 in I2Con, the user must set I2SCL, I2S yourself
The value in CH is set to set the data rate. I2SCH defines a high level of oscillating cycles, and I2SCL defines the low oscillating cycle.
The frequency is determined by the following formula: bit frequency = oscillator cycle / (I2SCH I2SCL) I2SCH, I2SCL is not necessarily the same, and the user can set the duty cycle of two registers. Storage
The content of the device guarantees that the I2C data rate is 0-400 kHz, so the two accumulators have some restrictions, and the table recommended below
176.7.6 Main Transmitter Mode I2CON Address: 91h I2en Sta STO SI AA
CRSEL - 1 0 0 0 0 - bit
Rate is initially in this state in the mode. The serial data is transmitted via the P1.7 / SDA output, and the output serial clock is output with P1.6 / SCL output, the first word sent.
The connotation includes the address (7 bits) of the slave and the data direction bit, the data direction is 0 in this mode, that is, transmitted to W, so
A sending byte is SLA W, serial data sends 8 bits, and receives a response bit every byte, starting
Start and termination conditions are used to represent the start and end of the frame transmission. 6.7.7 The first byte transmitted by the main receiver mode includes a receiving device from an address data direction bit, which is 1 in the data direction, transmission.
For R, this is sent to SLA R, and the serial receives 8 bits once, and each receives one byte returns a response, start and terminate the start or end of the flag serial transmission. 6.7.8 Sending data from the receiving mode serial data and serial clock to receive data by P1.7 / SDA, P1.6 / SCL, receive a response to one byte transmission
Bit, start and stop bits are used to log the start and termination of serial. After accepting the direction of the address and transmission, through hard
The item is implemented. 6.7.9 Send and processing from the first byte of the transmitter mode is the same as from the receiver mode, but in this mode, the direction position indication is opposite.
The serial data is output with the P1.7 / SDA output and the clock data is used by P1.6 / SCL input, start and stop bit to sign serial line.
Start and termination. 7. 8 Watchdog Watch Dog Clocks System protects the microprocessor to automatically reset after performing the error code for a while, when watching the door
The clock will take the end of the clock in due to the software error. The watchdog clock of P87C51MX2 is completely compatible with 89C51RX2, and the proportional coefficient of 1024 is added (default status)
Under the no proportional coefficient), the timeout mechanism of longer-time hooded dog is supported. WDT is made of 14-bit records and watchdog clock special registers, the proportional coefficient can be controlled by the WDCON film special register
system. 6.8.1 Watchdog Function The internal watchdog timing clock calculation formula is as follows: Timeout = 16383 * Proportional coefficient * 6 / oscillator cycle In other words, after the watchdog assignment, it is necessary to pass the 16383 * proportional factor. Watchdog reset
Unless the period is reloaded before the timeout.
6.8.2 Watchdog Assignment WDT is not available after reset, the user must put the WDTRST register to load 01eh, 0e1h can activate the watchdog
Once the watchdog is activated, the user must keep the register content before the timeout will prevent the watchdog over.
Out. Once overflow, a driver reset high pulse will be generated by the RST pin. If the WDT is activated, unless the reset is
You can't close the watchdog. The following code is recommended to load the watchdog content. CLR EA; Close all interrupts to prevent interrupt processing MOV WDTRST, # 01EH; load the first part of MOV WDTRST, # 0E1H; load the second part setb EA; turn on all interrupts: 1. Incmity or reset The reset of the watchdog will make the dog don't work, then you need to re-
Loading makes the watchdog up, unless the reset is reset, the watchdog does not work. 2. Toned dog passed
Since then write 01eh, 0E1H is activated after 0e1h, and anything different from the input 1EH will not be seen.
Door dog reset, once any content different from 01eh or 0e1h after writing 01eh, writing registers will cause watchdog
Reset 3. The trigger time on the WDT open is generated after the E1H is written to WDTRST. 4. Figure 62 shows the WDT operation, including the form of a non-specified load register 6.8.3 WDT control P87C51MX2 has a control register in the external special register space, 3 proportion of factor bits to choose the door
The scale factor of the clock, WDCON needs to be loaded before the WDT is started. If WDCO is loaded if WDT is activated
N can lead to unpredictable behaviors. 6.8.4 Watching Dog Reset Width When the watchdog overflows, a reset will be generated, and the external RST pin is driven by the 98 clock cycle to drive the WDCON address: 8FH WDPRE2
WDPRE1 WDPRE0WDCON.2-0: Used to choose a proportional factor - WDPRE2 WDPRE1 WDPRE0 PRESCALE FACTOR0 0 0 10 0 1 40 1 0 160 1 1 641 0 0 1281 0 1 2561 1 01 5121 1 1 10246.8.5 Read WDCON content Note that WDCON content is not meaningful after writing, only the old data written on, only when WDTRST is loaded after being loaded, can read to the correct current data. 6.8.6 Resetting the instruction below by watching the door dog will reset the software mode by reset by the loading of the watchdog, even if it occurs
Do not affect the execution of the reset function, MOV WDTRST, # 01EH; load 1EHMOV WDTRST, # 0AAH; any value that does not equal to 1Eh or E1H can cause a reduction of aah6.9 AUXR Address: 8EH Reset value: 00h
Extram AoAuxR7-2 Reserved AuxR.1 Extram is used to select internal / external addressing RAM for MOVX @ RN / DPTR
The effective bit of the area, if 0, the chip will take the interior RAM addressing, of course, if the data behind Movx exceeds the internal address
The district will go to the external RAM addressing. If 1 will go to the external RAM to address. AUXR.0 AO ALE control
Use the setting ALE to turn on the function, if 0, the ALE performs a constant magnification of 1/2 of the transmission cycle period, if 1 occurs
The latch function is performed at EMOV MOVX MOVC.
6.9.1 Expanding Data Area Addressing P87C51MX2 expands external addressing capabilities, detailed data storage structures are described with respect to the 51mx structure. Device's in-chip storage map The following sections 1. 0000H - 007FH Direct or indirect addressing area 2. 0080H - 00ffH is an indirect addressing area (iData memory) Note that 0000H - 007FH directly
SFRS can be directly accessed 3. 0100H - 01ffH (for MB2 / MC2) External indirect addressing area is EDATA MEMORY4. XData has 1536 bytes (positioning 0000h-05FFH) for MB2, and 2560 bytes (positioning
0000H-09H) for MC2, if extram = 0 internal xData zone data either use 0000H-05FFH MB2 or
0000H-09FFH MC2, external addressing also follows the above settings. If extram = 1 then internal xdata ram is not
Can be used to address external data anywhere. The Hungou RAM address described above is effective for the MX2 part of the p87c51mx2, and the early MX tag part is looking for
Some of the subplates are slightly different. 1. 0000H-04FFH (for MB2 / MC2) is an external indirect addressing RAM2. The same xData is 768 bytes (0000H-02FFH) for MB2,1792 bytes (0000H-06FFH) for MB2,1792 bytes.
MC2. Regardless of the old or new, the user can provide RAM, the old code can be re-new in the new
Compile, variables in the address space higher than 01ffh in EDATA should be moved to part of XDATA. 6.9.2 Double Data Pointer Dual DPTR is added to perform special address addresses for the corresponding instructions, and the DPS bit in the AuxR1 register is used to select
A DPTR, the currently not selected DPTR is not affected by the software if the DPS bit is fixed. Inc DPTR; DPTR's self-incremental operation JMP @ A DPTR; jump to the DPTR address A content size of MOV DPTR, # data16; assign 16-bit value to DPTR to MOVC A, @ a dptr; Code area find DPTR A Address MOVX A, @dptr; take data into amovx @dptr, a; put data, the same read instruction or use DPH, DPL to operate the current DPS must first set a DPS bit to select a DPTR, AuxR1 is always Keep 0, so set the DSP as long as it is simply incremented by AuxR1, do not pass possible
Changing the other bit of this register is implemented. 6.10 Programmable Radio Matrix does not use it slightly
