Chapter 6.P89C669 port, power control, and peripherals Note: Special register access There is a certain limit 1. If it is not defined, it is not possible to be accessed 2. must be set by setting the register in accordance with the function of special registers 3. Special The register flag must read and write in the following rules' - 'must write 0'0' write 0 readout Return 0 '1' write 1 readout Return 14.6.2 P89C669 port 6.2.1 Port 1 2 3 4 These ports Just like the traditional 80C51 device port, they have the same set bit address in the special register address space.
In: 80h 90h A0H B0H View port output is logical and port special registers and microcontrollers use this port, in order to make peripherals
Fully control a specific pin, the corresponding special register bit is set to 1, if these special registers are 0, then
The peripheral device cannot use these pins to output because the bit of the register is always 0.6.2.2 port 4p89c669 expands a port 4. This port is invalid for the general output output. He is used to use the UART1 to use P4
.0 (RXD1) and P4 .1 (TXD1), both have built-in pull-up resistors. 6.3 Low Power Mode 6.3.1 Clock Off Mode This static design can be reduced to 0Hz, when the oscillator stops, RAM and SFR maintain the original value, this
Mode uses and allows reducing constant frequencies to reduce system power consumption, is recommended by default for the lowest power power-down mode
. 6.3.2 Idle mode In idle mode (Table 11) CPU keeps sleep state does not work, but the equipment in the film is activated, in idle mode
After the last instruction that is activated in the normal mode of operation, the CPU 12 is kept correctly.
During the idle period, the idle mode setting is set by the IDL bit in the PCON register. There are two ways to end idle mode, and any interrupt request causes the IDL bit to be cleared, and the idle mode is ended. Interrupt
Services, then jump out of the interrupt, and then follow the execution of the hardware idle mode instruction. The reset of the hardware is the second way to end the idle mode, and continue to process in the same way in reordering
After moving, the IDL bit will be executed by the default flag to 0, and some finger will be performed before the real reset and reset operation control.
Once the idle mode is set, it is to resume the execution in the program, and the in-slide RAM is restricted during this period.
However, getting the port tube foot is not limited, it is recommended to add 2 NOP instructions after setting the space mode command,
Eliminate some unexpected port output, tightly followed by calling the idle mode, is not written to one end
The hobules or external memories. 6.3.3 Power-down mode In order to save more energy, a power-down mode can be called set by software (Table 11), in this mode, shock
The wheel stops, calling the power-down mode command is the last instruction, this mode is turned off the oscillator to achieve the most
Small power consumption, power-down mode is set by the PD bit in the PCON register. MODE Program Memory ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power Down Internal 0 0 Data Data Data Data Power Down External 0 0 Float Data Data Data table 116.3. 4 The power-on flag is powered by the inner circuit setting when VDD and P89C69MX2 are also rising to 0V, and the power-on flag is used to use the decision.
No, it is up to reset or hot start after power failure. The POF bit can only be cleared by the software. 6.4 Timer / Counter 0 and 1 Two 16-bit / count registers: Timer0 Timer1 can be set as a timing or event counter function (figure27), the register each machine cycle will increase, so we think he can record the number of machine cycles ,
Because a machine cycle consists of 6 oscillating cycles, the recording magnification is 1/6 oscillating divide. Under the count function, the register will increase the self-increment response from 1 to 0 hopping at the corresponding external input pin, T0 or T1 at each
The machine cycle is the external pin input fixed signal sampled one count change requires two machine cycles, as the previous machine cycle is displayed sampled as a positive date display sample
In response, it is determined that it is a falling edge, triggered the counter count, and there is no limit for the external input signal, but
It is to determine a standard sample before it changes, it saves a complete machine cycle, except for timing and counting
Outside the device, the timer has four ways of working. 6.4.1 Mode 0 Set the clock interrupt to 0 mode It looks more like 8048 clock interrupt, and an 8-bit counter uses 32 as a factor.
Figure 29 to display the timing mode operation In this mode, the clock register is configured to 13-bit registers, when the count is turned from 1 to 0, the timing flag bit TFN
Will be set, record input activation timer When TRN = 1 and Gate = 0 or INTN = 1. Set Gate = 1
Is the external input pin INTN control timer, easier to measure the pulse width), TRN is controlled by special register TCON
Drawing 28, Gate is controlled by the TMOD register. The 13-bit register consists of 5 digits of 8-bit ThN and TLN, and the other three bits of TLN are uncertain and should be ignored. Set
The execution flag TRN does not clear these registers. Mode 0 is the same Fig. 29 for timing 0 and timing 1, only two different Gate bits, TIME0 (TMOD.3) TIM
ER1 (TMOD.7) 6.4.2 Mode 1 Mode 1 and mode 0 are basically the same, except that the clock register becomes 16 bits (TLN8 bits) TRN Figure 306.4.3 mode 2 mode 2 automatically configure the clock register to 8 Bit TLN, as shown in Figure 31, the overflow in TLN not only affects the content in the TFN
The contents of the contents in TLN are also reset, which must be adjusted by software in advance. This reset
Will not change the content of this. Mode 2 is the same for Timer0 TIME1. See Figure 31 Figure 316.4.4 Mode 3 When Timer1 is set to mode 3, it will be turned off (hold the count function), set TR1 = 0 setting timing invalid
The same effect. When Timer0 is set to mode 3, then TL0 and TH0 are two separate 8-bit count registers, mode 3 logic control and TI
MER0 setting is as shown in Figure 32, TL0 uses TIMER0 control bits: T0C / T, T0GATE, TF0, TH0 is due to the auxiliary circuit
The lack of only one timer can be used as an 8-bit, and also borrows T1 start, stop the switch TR1 and overflow flag TF1, because
T1 is borrowed, so T1 cannot constitute this mode 6.5TIMER2TIMER2 is a 16-bit timer / curler can be used as an event timer or a numeric, which can be used by special registers.
C / T2 in T2CON can be selected. Timer2 has four working methods: capture, automatic reset (increasing or decreasing)
Number, clock overflow, normal baud rate. The choice of work mode is controlled by T2CON and T2 MOD. As shown in Figure 33 and 34RCLK TCLK CP / RL2 TR2 T2OE MODE 0 0 1 0 16 - Bit Auto Reload 0 1 1 0 16-Bit Capture 0 0 1 1 ProgramMable Clock-Out 1 x 1 0 Baud Rate Generator for Uart 0 x x x x x 0 X OFF Table 126.5.1 Capture Mode Can have two options in the capture mode by controlling the Exen2 bits in T2CON, if the Exen2 bit is 0Timer
A 16-bit counter or timer, overflow bit is TF2. This bit can generate an interrupt by activating Timer2
The interrupt bit in the register IEN0, if exen2 = 1, Timer2 works like a picture below, but increases the characteristics such as
When the external pin T2EX input signal is from 1 to> 0, it will cause the current T2 register capture mode, and TL2 TH2 will be captured.
RCAP2L RCAP2H. Figure 35. In addition, the input hopping of the T2EX pin will cause EXF2 bits in T2CON to be set, EXF2 and TF2 will generate one
Interrupt (and overflow interrupt vector settings), Timer2's interrupt service road tour will review the EXF2
It is TF2 application interrupt service. There is no reloading TL2 and TH2 here. When the capture event is generated by EX2T, the counter holds the T2 pin count or f (O "
SC) / 6 pulse, since the content of RCAP2L RACP2H will not be protected once the contents of the RCAP2L RACP2H, once the TIMER2 interrupt request
Then you must create capture events in a new EX2T pin, otherwise, the next T2EX pin will take
Dissipose the current TL2 and TH2 to RCAP2L and RCAP2H registers, the result will destroy the content related to the previous interrupt report.
. Capture Mode can be seen in Figure 366.5.2 Auto Reset mode In 16-bit automatic reset mode, Timer2 is set to the timer or counter through C / T2 in T2CON.
Then determine the increase in program count or decrease, how to count will be Decn in the register T2MOD (notified down)
Bit settings are determined. When reset, DECN = 0, Timer2 default count is an upward growth method, if the DCEN bit is
Setting that the decision will be determined by the value of the T2EX pin. Figure 36 shows the TIMER2 automatically record (DECN = 0) this mode, there are two options to set the Exen2 bit in the T2CON register, if Exen2 = 0 is the counter
The upward record to FFFFH will generate overflows, automatically set TF2 bits, then generate Timer2 to RCAP2L and RCAP2H
The content is loaded into TL2 and TH2, and the content of RCAP2L and RCAP2H is pre-set by software, and the frequency loaded.
Can be calculated by this formula: SupplyFrequent / (65535- (RCAP2H, RCAP2L)) SupplyFrequent either F (OSC) = 0 (C / T2 = 0) or T2 pin C / T2 = 1 If Exen2 = 1,16 Reset is initiated by overflow or T2EX pin by 1- "0 hopping, this hop will also be
From the setting of the EXF2 bit, the first clock cycle T2EX pin sample is 1, the second clock cycle sampling bit 0 So EXF2
It will be set to 1, and the timer generating interrupt If the setting is valid, it will be generated when the TF2 or EXF2 bits are set to 1. The processor requires a continuous three machine cycle to identify the falling edge, the first machine cycle is sampled from the T2EX pin, the second machine cycle pin samples 0, and the third machine cycle sets EXF2 = 1 Figure 37, DCEN = 1 and the clock 2 can be set up or down, allowing T2EX pins to control
The direction of the number, if the T2Ex logic is 1 will set up the upward, Timer2 will overflow when fffh and set the overflow bit T
F2, to generate an interrupt, this interrupt also produces RCAP2L RCAP2H capture content to reload TL2
TH2. When the T2Ex logic is 0, the record is down, then the data in TL2 and TH2 and RCAP2L and RCAP2
When the content in the H is equal, an overflow interrupt is generated while reloading the FFFFH in TL2 and TH2. EX2-bit
It is defined to indicate overflow or down, and EXF2 can also be expressed as the 17th bit. Figure 376.5.3 Programmable clock overflows half of the clock cycle output to T2 foot (P1.0), P1.0 In addition to the standard I / O pin, there are two extensions: 1. Enter external clock as timing Under the operating frequency of 16 MHz, outputting a frequency of 50% of the frequency between 122Hz and 8 MHz ranges, a timer / counter as a clock generator, the C / T2 bits in T2CON must be cleared , T2 in T2MOD
The 0e bit must be set, T2CON. 2 (TR2) must also be set to initiate the timer. The clock overflow frequency depends on the value of the oscillating frequency and reloading the T2 capture value (RCAP2L, RCAP2H), you can look at this
Equation: OscillatorFrequenty / 2 * (65535- (RCAP2H, RCAP2L)) (RCAP2H, RCAP2L) is the value of RCAP2H, RCAP2L two unsigned registers. In the clock overflow mode, T2's hop does not cause interruption, which is similar to the use of a baud rate. 6.5.4 UART0 baud rate generator mode When the port is a separate baud rate generator (Sobrgs = 0, brgscon.1), TCON in TCON or RCLK bit
Allow transmission and reception baud rates from T1 or T0. Assume S0BRGS = 0, when TCLK = 0, Timer 1 as a UART
0 Transport baud rate generator. When TCLK = 1 timer 2 is transmitted as a UART0 transmission baud rate generator. RCLK and TCLK are not
Use more, just the timer is changed to UART0 receiving baud rate generator. Below 38 is the baud rate generator mode baud rate generator mode is like an automatic load mode, and when TH2's hop will cause Timer2 to reload to RCAP2L,
RCAP2H pre-set content. The baud rate generator is determined by the benefit rate given by T2 in mode one and mode.
. The baud rate of mode 1 and mode 3 = oscillator frequency / (16 * (RCAP2H, RCAP2L))) (RCAP2H, RCAP2L) is a 16-bit shaping constituent. Timer2 As the baud rate generator only when RCLK / TCLK = 1 is meaningful, pay attention to the jump in TH2 does not set at this time.
Set the TF2 bits, do not cause interrupts, so when Timer2 is set to the baud rate generator, there is no need to close the corresponding
Break setting. Also if Exen2 is set, 1-0 hopping causes the input of the timer / counter, will cause EXF2 (T2
External flags are set but will not cause overload, so when T2 is used as the baud rate generator, T2ex needs to be used as an external interrupt. When T2 is used as the baud rate generator mode, it is best not to read the TH2 TL2 separately, read and write TH2, TL2 under this condition.
It may be inaccurate, and the RCAP2 register is readable, but don't write, this may generate a repetitive
Loading causes write or reloading errors, Timer should be closed (TR2 clear) is needed to get T2 or RCAP2
Previously, Table 13 shows the use of baud rate generators and how to get Timer26.5.5 baud rate formulas Timer2 is set to the baud rate. If Timer2 is used through T2 (P1.0), then the baud rate Plan
Calculated: baud rate = clock overflow rate / 16 If the clock 2 is obtained by internal counting ratio = F (OSC) / (65535 - (RCAP2L))) F (OSC) is a frequency acquisition of the oscillator RCAP2H, RCAP2L Calculation Formula: RCAP2H, RCAP2L = 65535 - F (OSC) / (16 * baud rate)
