2.3 Special Function Registers
Special Features Registers provide a processor to access internal control registers, peripherals, and I / O ports. A special function register address is always included in an instruction.
Standard special function register space is 128 bytes. In order to provide control or access CPU characteristics and functions of peripheral devices, special function registers are implemented in each 51mx device. Unesented special function registers are treated as reservations and should not be accessed by the user program.
16 addresses in the special function register space are parabletable and bit addressing. Special function registers of the replaceable address are those ending at 0h or 8h (that is, 80H, 88H, ..., F8H). Bit address allows you to directly control and test the bit of those special function registers. All 51mx devices also have additional 128-bytes of extended special function registers (discussed in the "51MX Architecture Reference"). Figure 8 and 9 show map maps for special function registers and extended special function registers for P89C669 parts.
Figure 8
Figure 9
2.4 External Data Storage (XDATA)
The 51mx XDATA space is the same as the 64KB external data storage space on the classic 80C51.
The in-chip xData storage can be disabled under program control via the AUXR register's EXTRAM bit. Accessing the above implementation In-chip XDATA will be guided to the external bus. If the on-chip XDATA storage is disabled, all XDATA access will be booted to the external bus. P89C669 has a 768-byte piece of XDATA.
2.5 High-end Data Storage (HDATA)
The 51mx architecture uses 23-bit addressing to support 8MB of data storage space. The remaining 8MB space except 64kb EDATA space is referred to as HDATA. The xData space contains the low 64KB of HDATA.
The data pointer 51MX adds a 23-bit extended data pointer (EPTR) to allow convenient to expand the existing 80C51 program to allow more than 64 kb data storage. If we want to access a separate data byte located in the HDATA RAM in the first 64KB of the first 64KB, the EAM bit must be set (EAX = 1).
All 80C51 instructions with DPTR have a 51mx variant using EPTR. 23-bit EPTR consists of (sequential) Eph, EPM, and EPL special function registers. Figures 10 and 11 show examples of indirect access to data storage using DPTR and EPTR, respectively. Because EPTR is 23 bits, the 8th digits of EPH are not used. If reading, it returns 1, like other in the special function register, the same is not implemented. EPTR can be operated as a 23-bit register or 3 separate 8-bit registers. Use EPTR to allow access to the entire HDATA space, including xData. At any time, a specified data pointer is active and is used with DPTR-related instructions. The active data pointer (DPTR) consists of a high byte (DPH special function register) and a low byte (DPL special function register), and its purpose function is to save a 16-bit address; however, it can be Take a 16-bit register or as two independent 8-bit registers. The selection of the active DPTR can be changed by changing the data pointer selection (DPS). The DPS bit takes up the optimum of AuxR1. DPS bits are only applied to two DPTRs, not EPTR.
In indirect addressing mode, the current active DPTR or EPTR provides a data storage address for accessing XDATA and HDATA, respectively. When DPTR is used to address, only XDATA space can be obtained. When the EPTR is used to address, the entire HDATA space (including xData space) can be accessed. If the EPTR value exceeds 7E: FFFF (HDATA limit), data access using EPTR can cause undefined results. Limiting the HDATA address to maintain the addressing unity of the EPTR addressing and general pointer addressing (in the back of this article). Figure 10
Figure 11
2.6 Program Storage (CODE)
80C51, of course, there are 51mx, all "Harold" architecture, means that the code and data space are separated. If a byte of an executable code is exceeded 64KB, then the EAM bit of the MXCON special function register must be set (EAM = 1). Similarly, there is a constant in Code exceeds 64KB boundaries, and this constant is read by the application, then the EAM bit must be set (EAM = 1).
The 51mx architecture extends the 80C51 program counter to 23, provides a continuous, no segmented linear code space, which may have 8MB. The internal space starts from the code address 0, extends to the boundaries of the on-chip code storage. Beyond this limit, the code will be taken from the tablets. 51mx architecture optional external bus, it supports:
· Mixed mode (some of the external code and / or data storage)
· Single-chip operation (no external bus connection)
· No ROM operation (no single-piece code storage)
In some cases, the code store can be addressed as data. The extended instruction addressing mode can access the entire 8MB band code space by using an indexed indirect addressing. The current active DPTR, EPTR, general pointer or program counter can be used as a base address. Figures 12 through 24 show examples of different code storage addressing modes.
After reset, like a classic 80C51, P89C669 starts code from the address 00: 0000H. Similarly, the interrupt vector is placed on the reset address, starting from the address 00: 0003H. It should be noted that the first instruction (at address 0) should not be an EJM instruction. EJMP is a 5-byte instruction, which will overlap the external interrupt vector 0 at address 00: 0003H.
2.7 Universal Pointer
In particular, in a large program enhances the code density and performance of the C language, a new addressing mode is called universal pointer mode has also been added to 51MX. This addressing mode allows you to use a directive to access any piece of code and data space outside the on-chip without further know which one of the data is in different spaces. This includes Data, IDATA, EDATA, XDATA, HDATA, and CODE space. The SFR space is the only space that cannot be accessed using General Pointer.
General pointer addressing mode uses a new pointer register set, there are two reasons here. The first is to allow addressing 8MB of code space and 8MB data space, requiring a 24-bit pointer; the second reason is that the multi-byte data in the operation register is more effective than the SFR. The C compiler is actually a pointer operation in the register, and then moves the result to the data pointer to use.
Supports two general pointers: PR0 and PR1. The PR0 pointer consists of registers R1, R2, and R3 in the current register "stack", and PR1 consists of registers R5, R6, and R7 in the current register "stack". See Figure 15.
In order to access all different storage spaces through a single and unified manner, these storage spaces must be mapped to a new 16MB total storage space. This new view is called a universal storage mapping. The XDATA space is placed at the bottom of the new address map. HDATA space is tight of XDATA. Standard internal data storage space (DATA and IDATA) on the top of HDATA, behind the remaining EDATA space. Finally, the code storage space occupies the top part of the map. Therefore, the maximum active bit of the general pointer determines the access code or data storage. By placing the XDATA space at the bottom of the universal storage map, the general pointer from 00: 000H to 00: FFFFH address can be consistent with the external data storage space of the classic 80C51. This provides complete upward compatibility in the code of more than 64KB external data space. Figure 16 shows a universal storage mapping, and Figure 17 shows the standard storage space and how the value of the universal pointer is only 51mx's instruction called EMOV. The EMOV instruction allows data to move data or removed through a general pointer. Whether it is movement or removing, it can be specified for the offset of 0, 1, 2 or 3, which will add the pointer used in front. The offset allows the C compiler that does not have to change the value of the pointer, you can access the maximum variable (such as long integer). Figure 18 shows an example of a general pointer usage. Note that the Code area saving value in the universal storage map is not possible. Another new instruction that is added allows us to add a general pointer to the value of 1 to 4. This allows the pointer to the last data element that is last accessed, and points to the next data element. The general pointer is mainly designed to facilitate access to the addressing mode (when the bit EAM in MXCON is set). The general pointer can then be used when EAM = 0 is used. In this case, universal pointer addresses only 64KB code spaces under the bottom, and 64KB XDATA space under the bottom. The value pointing to the general pointer to these areas cannot be changed. When EAM = 0, when the general pointer accesses an unacceptable area other than these areas, the value is returned.
