2.1 Program model and storage mapping
P89C669 maintains all 80C51 storage space. Additional storage space is also added as part of the transparent, allowing extended addressing. The basic storage space includes code storage space (which can be outside or both or both), external data storage space, special function registers, and internal data storage space (including internal RAM, registers and stacks), Adredient is used as an extension of internal data storage, allowing a larger processor stack.
The following figure shows the program model and storage mapping of P89C669:
Figure 3.
Graphics three
The following list describes the different parts of 51mx storage space:
The internal data storage space (00h ~ 7FH) of the DATA 128 bytes can be accessed by other instructions in addition to MOVX and MOVC by direct or indirect addressing. All or part of the stack can be placed in this area.
Idata indirect data (Indirect Data). 256 bytes of internal data memory space (00h ~ ffh) can be accessed by indirect addressing, other instructions access to MOVX and MOVC. All or part of the stack can be placed in this area, including the DATA area and 128 bytes here.
EDATA extension data. This is a supercoming of Data and Idata. P89C669 has 1280 bytes of SRAM in the EDATA storage space. This additional area can be used as a stack access, by using the universal pointer indirect addressing. The stack can be placed in an extended area, if this can be done. EDATA's content can be accessed at any time using the EMOV instruction, regardless of the bit EAM in MXCON.
SFR Special Function Register. Includes the selected part of the CPU register, peripheral control, and status register, can only be accessed by direct addressing (addressing range at 80h ~ FFH). This also includes new 51mx extension special function registers.
XDATA external data (External Data). Like the classic 80C51 64KB storage space, you can pass the MOVX instruction and access it using DPTR, EPTR, R0 or R1. The XDATA in the tablets can be disabled under the control of the program. Similarly, XDATA can also place an external device. P89C669 has a 768-byte slice of XDATA storage.
HDATA High Data (High Data). This is an ultra-set of XDATA, which can include storage space up to 8, 323, 072 bytes (8m to 64kb), and can be accessed by the MOVX instruction and using EPTR, DPTR, R0 or R1. The non-xdata portion in HDATA is placed outside the equipment.
The internal code storage space (0000H ~ FFFH) of Code 64KB is used to store program storage and data (via MOVC instruction).
Ecode is up to 8MB code storage, which can be accessed as part of the program execution or via MOVC instruction.
All of these spaces in SFR can also be used with EMOV instructions to access the addressing method of the general pointer. This feature is detailed in the later section.
TABLE 1
Memory size (bytes) and mx universalmemory map Range
Type Description p89c669
Data Data Memory That Can Be Addressed Both Directly and Indirectly; Can Be Used AS Stack 128 (7F: 0000-7F: 007F)
IDATA superset of DATA; memory that can be addressed indirectly (where direct address for upper half is for SFR only); can be used as stack 256 (7F: 0000-7F: 00FF) EDATA superset of DATA / IDATA; memory that can be Addressed Indirectly Using Universal Pointers (PR0, 1); Can BE Used As Stack 1280 (7F: 0000-7F: 04FF)
XData Memory (On-Chip "External Data") That IS Accessed Via THE MOVX INSTRUCTIONS USING DPTR / EPTR 768 (00: 0000-00: 02FF)
Code Code Memory Used for Program Storage and Data Access Using Movc And Emov 65536 (80: 0000-80: FFF)
Ecode Code Memory; Data Access Can Be Accomplished Using Universal Pointers (PR0, 1) And EMOV 98304 (80: 0000-81: 7FFF)
Table I
2.2 Data Storage (Data, Idata and EDATA)
The standard 80C51 internal data store consists of 256-byte DATA / IDATA RAM, which is generally in the case. In this space: data register (R0 ~ R7), default stack, a point of addressable RAM area and general purpose data RAM. At the top of the DATA / IDATA storage space is a 1024-byte RAM block, which can be accessed as a stack or via indirect addressing. This forms 1280 bytes of EDATA RAM together. Different parts of the data store are described in the following sections.
2.2.1 Register R0 ~ R7
General purpose registers R0 ~ R7 allow fast and efficient access to some internal data storage. For example, this directive:
Mov A, R0
Only one byte code is used and only one machine cycle is performed. Use direct addressing to complete the same result, such as:
Mov A, 10h
There is a need for two bytes of code storage and execution time of two machine cycles. Indirect addressing also requires some set of pointer registers.
These registers are "Bank), that is, four sets of registers, any group can be selected to indicate when it is appropriate from R0 to R7. The desired register "stack" is selected using the bit RS1 and RS0 in the PSW special function register. This feature can be used to minimize the time of the context environment switching of the interrupt service or subroutine, or provide more register space for complex algorithms.
The register and other internal data storage situations are not different, except that they can be addressed by "speed notes" symbol, such as "R0", "R1", etc. In other words, the instructions to address internal data storage, such as direct or indirect addressing, fully accessible as the same physical storage location in any of the four "stack" in any register group.
Table2
RS1 RS0 Bank Memory Segment In Data
0 0 Bank 0 00h ... 07h
0 1 Bank 1 08H ... 0FH
1 0 Bank 2 10H ... 17H1 1 Bank 3 18h ... 1FH
2.2.2 RAM that can be addressed
The internal data storage area 20H to 2FH can be accessed as bytes and bits. This provides an aspect, an effective way to operate a separate marker without using a lot of storage space. The byte of the most under the bit is at the address 20H, the bit number is 00h, the next bit is in the same byte, the bit number is 01h, etc., the last bit, that is, the bit of the 2fh byte 7, the bit number is 7FH (127). The bit number mentioned above is related to the median of the special function register.
This code:
Setb 20h.1
CPL 20H.2
JNB 20H.2, Label1
The bit 1 (set) of the address 20h is set, and the bit 2 (claim) of the same byte is completed, and then the branch (jump) if the second bit is not equal to 1. These bits are usually given to some names in the actual program and provide to the bit operation instruction.
2.2.3 Expanding Data Storage (EDATA)
The 51mx architecture allows an extension to the internal data storage space to exceed (80C51 classic) 256 byte limits. This space can be used as an extended or optional processor stack space, or can be used as a general purpose storage under the control of the program. In addition to the stack pointer to access (see the section below the stack storage mode) This space can also be addressed in this space. The general pointer is described in later section.
2.2.4 Stack
The processor stack provides a method to save the return address of the interrupt and subroutine, and temporary data. The stack is growing up (the translator's note: the PC is generally growing down), from a lower address to a higher address. The current stack pointer always points to the data that is finally pressed onto the stack, as long as the stack is not available. The forward stack operation, the stack pointer value is incremented, and the data is written to the memory. When the stack is put, the opposite process is used. First, the data is read from the memory and then the stack pointer value is decremented.
The default configuration of the 51mx stack and the classic 80C51 are the same. When the interrupt or subroutine address is pressed into the stack, only the program count is lowered by 16 bits. In the figure below, this default 80C51 mode is displayed:
Figure 4
For stacks, there are two configuration options. In order to be backward compatible with the classic 80C51, the two additional modes are prohibited when the chip is reset.
The first option, the extension interrupt mode, make the interrupt to press the entire 23-bit program counter into the stack (press 3 bytes), and make the RETI command to pop up the entire 23-bit mature memory as a return address, in Figure Figure 5 in. The high position of the stack byte containing the highest valid byte of the program counter is enforced to 1 with the universal pointer addressing.
Because an interrupt can occur in any point in the program, it is necessary to store the entire 23-bit program counter value, which includes more than 64KB programs. The expansion interrupt mode only changes the operation of the interrupt and RETI instructions, other calls and returns have not been affected. Special extension calls and return instructions Allow large programs to use the entire 23-bit return address to move back and forth throughout the code space. Use the EIFM bits in the MXCON register to turn on the extension interrupt mode mode.
Fighe 5.
The second stack option, the extended stack storage mode, allows the stack to expand, more than 256 bytes of the classic 80C51 family. Stack extensions are implemented by increasing the stack pointer to 16 bits and allows it to address the entire EDATA storage area (not only standard 256-byte internal data storage space). The stack extension does not affect the data stored on the stack, which will continue to be saved, see Figure Figage 4 and 5. Turn on the extended stack memory mode by setting the ESMM bit in the MXCON register. If the stack pointer is not initialized by the software, the stack begins with the address 8 of the in-slice, like 80c51. Also pay attention to extended stack storage mode, P89C669 section has 1024 bytes of RAM space on top of the DATA / IDATA to be a stack.
Stack mode bit ESMM and EIFM are displayed in Figure Figure 6. Note that during the initialization of the program and there is no change in the stack mode bit in that future, the stack mode bit is set. Dynamic change stack mode will cause stack synchronization problems.
2.2.5 MX Control Register (MXCON)
The microcontroller's MX family is developed in such an idea that provides an 80C51 user that allows applications to grow in different directions. When improving many features, you must maintain a complete and previous compatibility.
There are two main improvements, one is the internal resource that can be identifiable, one is the microcontroller external address and data bus interface.
The MX2 section, and the previously compatible microcontroller compatible with 80C51, brings more available on-chip code and data space. In order to make these improvements, the MX specific characteristics are added, and the instruction set is also enhanced accordingly.
The MX Control Register (MXCON) determines the operation mode of 669. It is not recommended to change the register in the application execution, although this is possible. The structure of MXCON is displayed in Figure Figure 6. Use the bit EAM, there are two operating modes that can be used.
EAM = 0
After reset, bit EAM = 0 (default) makes the P89C669 part in a fully 80C51 binary compatible micro mode. It and the outside interface is a 16-bit wide address bus and an 8-bit wide data bus. The program counter (PC) is 16-bit wide, so the executable code inside the film cannot exceed 64kb address range. The MX is used to transmit the special instructions of the PC (such as EMOV) are limited to the lower 16-bit value of the PC. The high 7 bits are treated as 0. This is why the EMOV instruction cannot retrieve content from the internal code space of more than 64KB. If the code starts from the on-chip code space, there is no external code to be executed, and the address bus can only access the RAM within 64KB.
EAM = 1
The mode determined by EAM = 1 makes the interior code exceeds 64kB and can take advantage of 96KB of code space. The external storage interface is through standard 51 external bus: 16-bit address and 8-bit data bus. In this configuration, the program memory (PC) is 23-bit wide, and special attention is required when the EIFM (Extended Interrupt Frame) is configured. If the on-chip code exceeds 64KB and the code is interrupted, the EIFM must be set because the address of the interrupt command may be 01: xxxx type. When the PC spans 64KB, keeping EIFM = 0 will cause only 2 bytes of addresses to the stack. Therefore, after the calling interrupt service routine is completed, the RETI instruction will further indicate that the code is executed to 00: XXXX (since the two bytes bibly from the stack), this will result in unpredictable system behavior.
If the memory code space in the film is only used to store constants (such as lookup table), the EIFM can be set to 0, because the address of any executed code can be represented by two bytes, and only There is a need to put two bytes into the stack (for the P89C669 section, this is the default). If the code starts from the on-chip code space, then there will be no external code is executed; the address bus can only access the external RAM of 64KB. Since this mode is just a 16-bit wide address bus, even if the EMOV instruction points to a location exceeding 64KB, the external memory is recognized as 64kb as the address (00: xxxx) as 64kb.
Figure 6
The EAM bit controls the space of the Code / Ecode and XData / HDATA accessed. EDATA storage space can be accessed with EMOV instructions at any time, regardless of the value of the EAM bit.
2.2.6 General purpose RAM
Some internal data stores that are not used as special applications of registers, stacks, and bit addressing areas can be considered for use as a generic destination RAM and in any need.
The low 128-byte internal data storage (DATA) can be accessed with direct or indirect addressing. Direct addressing the address in the entire directive. For example, this directive:
Mov 32h, # 10
The value of 10 (10) will be saved at position 10h. The space directly addressed 128 or more will access special function registers instead of internal data storage.
Indirect Addressing Addressing Use the address of R0 or R1 in the current "stack" and use it to identify one of the internal data storage. The entire 256-byte internal data storage space (Idata) can be accessed by indirect addressing. For example, this instruction column:
MOV R0, # 90h
Mov A, @ r0
This will cause the content of 90H to be read into the accumulator. More general purpose RAMs can be reserved in low-end regions that can be accessed with direct and indirect addressing, which causes the stack to be positioned in high-end areas, which is typical for classic 80C51. For 51mx, the stack can be expanded or the storage range low of 256 bytes can also be completely removed.
Fighe.
