1.1 51 MX processor core
Philip semiconductor 51mx (memory expansion) chip is based on accelerated 80C51 framework, and executes 2 times the standard 80C51 device. The 51mx address space is expanded from the original 51 64KB limit to the 8M program area and 8M data space. Keep the compatibility of all 51 program code, users can reuse the previous 51 development tools to eliminate the need to transfer to a new platform. The bus structure of the 51mx maintains 80C51 allows you to continue using the 80C51 interface peripheral and special integrated circuit (ASIC), but different bus interfaces are required when taking the expansion addresses other than 64K.
51mx is very good after compatibility with 80C51, which can be ported to 51MX if there is almost no modification under the 80C51.
Below is a rough difference between the 51MX and 80C51 chip architecture:
1PC is 23-bit expansion from 80C51 original
2 Expand the data pointer: Expand the data pointer called EPTR in 51mx, which is incremented to perform access to data space greater than 64K.
3 Stack: Two independent wheel selection stack modes, one set of outstanding stack addresses caused by interrupts is 23 bits, two allow stacks to expand to larger memory space.
4 Instruction Settings: Expand a part of the addressing mode instruction to perform addressing of the expansion code space and data space.
5 Addressing Mode: Add a new addressing method for universal pointers to address all code and data area, except for special registers to use separate instructions. Use this model to improve program space and execution performance.
66 division
1.2 p89c669 microcontroller
The Flash control of P89C669 is based on a Philip semiconductor chip architecture. P89C669 has 96K Flash Program Space and 2K static data area, and the device is pre-installed into the programmable data matrix PCA, and the watchdog is used to configure different time range, and two full-duplex UART and I2C transmitted in byte. Bus interface.
P89C669 has stronger functions, higher performance and lower system loss. Provide an internal storage process and improve the combination of external storage management. P89C669 does not require a software work area, an increased program store allows the design engineer to better use the higher-level language improvement more complex programs such as C, without adapting to the traditional less than 64K programs store, this increase can effectively increase C at 64k below execution efficiency .
P89C669 has a non-variable Flash program storage, which can be programmed in parallel, online programmable and field programmable. ISP: If the system uses this app, the user can download the new code data. IAP: Users can take the program and re-brush the program, allowing a connection to remote remote remote control. The default is in the ROM instead of the boot settings for Flash online programming, and IAP is also used to use the ROM scaled cured program to erase Flash and override the flash.
51mx main feature
123 bits of program memory space and 23-bit data memory space. Linear addresses can support up to 8M bytes of programs memory and data storage after extending.
2 The program counter extends to 23 bits.
3 Stack pointer extends to 16 bits, so that the stack space can exceed 80C51 limit.
4 Use the newly extended 23-bit data pointer and 2 24-bit general pointers to access different spaces, greatly improve the efficiency of the C compiler.
5100% binary compatible classic 80C51, existing code can be reused.
624 MHz CPU clock, one machine cycle contains 6 clock cycles.
796k byte on the inner program flash.
The block data RAM of the 82K byte.
⑨ Programmable Counter Array (PCA).
⑩ 2 full-duplex enhanced UART. The byte high speed I2C serial interface (400kbit / s).
51mx main benefits:
1 Add the program / data address range to 8M bytes.
2 Improve the performance and efficiency of the C procedure.
3 is fully compatible with 80C51 microcontroller.
4 Provide a seamless good 80C51 upgrade method
5 is supported by the 80C51 development programming tool manufacturer
6 Reduce development cost reduction market development cycle
All characteristics
Completely static.
24MHz CPU clock, one machine cycle contains 6 clock cycles.
96k bytes of Flash can be implemented in System Programming (ISP) and in Application (IAP). 2k byte of the inner RAM.
23 program memory space and 23-bit data memory space.
4 interrupt priorities.
32 I / O ports (4 ports).
3 timers: timer 0, timers 1, and 2.
2 full-duplex enhanced UART with baud rate generators.
The byte high speed C bus serial interface (400kbit / s).
Frame error detection.
Automatic address identification.
Power control mode.
The clock can be stopped and restored.
Idle mode.
Power down mode.
Two DPTR registers.
Asynchronous port reset.
Programmable Counter Array (PCA) (compatible 8XC51RX ) contains 5 capture / comparison modules.
Low EMI (prohibiting ALE).
Containable propagander, you can get a watchdog timer for different time ranges. (Compatible with 8xC66X attached pre-proprigeriors),
80C51 and 51MX compatible feature
1 is fully compatible with the classic 80C51, all 80C51 code can be reused
2 The first line program and data address range expands to 8M
3 program counter and data pointer to 23 digits
4 stack expansion is 16
1.3 Logical Sign of P89C669
