Today, I'm doing an operating system test, INTEL manual discovered this command: CPUID used it, finally understand how to view the model number of the CPU and the specific parameters: You can see your code under the GCC. The model of the CPU: u_int val = 0; __asm __volatile ("xor% eax,% eax"); __ASM __Volatile ("inc% eax"); __ASM __Volatile ("cpuid"); __ASM __Volatile ("Movl %% EAX, % 0 ":" = b "(VAL)); Printf ("% x / n ", val); specific number of specific numbers and other parameters can refer to the following article:
CPUID instruction 1. CPUID instruction code: 0A20F case: {CPUID Macro DW 0A20FH endm} 2. CPUID Effective detection If the program can change the 21st bit of the EFLAGE (extended flag word), the cpuid is valid, otherwise it is invalid. Note: For Cyrix's CPU, use this method to detect invalid before opening its internal CPUID flag.
Example: {... Pushfd Pop Eax Mov ECX, EAX XOR EAX, 200000H; Forced Extended Sign Bits 21st 1 Push Eax PuPFD Pushfd Pop Eax XOR EAX, ECX; if the 21st bit of the expansion flag is 1, then JE NO_CPUID; CPUID exists, otherwise there is no JMP Have_cpuid ...} 3. CPUID command (1) Basic instruction 1. No. 0 function: (eax = 0) call register: EAX = 0 Return Register: EAX = Maximum function number EBX: EDX: ECX = CPU vendor recognition series example: {... xor eax, EAX; call 0 function cpuid; execute CPUID instructions CMP EBX, "Genu"; judgment EBX: EDX: ECX is "Genuineintel" JNE NO_INTEL If it is the CPU vendor Intel, otherwise it is not CMP EDX, "INEI" JNE NO_INTEL CMP ECX, "NTEL" JNE NO_INTEL JMP IS_INTEL ...} 2. No. 1 function: (EAX = 1) call register EAX = 1 Return Register EAX = CPU Description CPU Description (see Appendix 1) {BIT Content 0--3 Rate (Stepping) 4--7 Model 8 - 11 Family} EDX =
Signature word {bit content Abbreviation 0 FPU On-chip FPU 1 Virtual Mode Extension VME 2 Debugging Extension DE 3 Page Size Extension PSE 4 Time Stamp Counter TSC 5 RDMSR / WRMSR Instructions 6 Physical Address Extension PAE 7 Machine Check Exception MCE 8 CMPXCHG8B Instruction 9 On-chip APIC HardWare 10 Undefined 11 SYSENTER / SYSEXIT Instructions 12 Memory Type Range Registers 13 Page Global Enable PGE 14 Machine Check Architecture MCA 15 Conditional Move Instruction CMI 16 Page Attribute Table PAT 17--22 Undefined 23 MMX Instruc TIONS MMX 24 Internet Streaming SIMD EXTENSIONS SSE 25-31 undefined} (2) Extended instructions 1. Extra 80000000 (EAX = 80000000H) Call register: EAX = 80000000H Return register: EBX, ECX, EDX = preserved EAX = maximum function Number 2. No. 80000001 Function Call Register: EAX = 80000001H Return Register: EAX = CPU Description (See No. 1 function) EDX = Extended Feature Sign {EDX [0] <- fpu: FPU On Chip EDX [1] < - VME: Virtual Mode Extension Present EDX [2] <- De: Debbuging Extions EDX [3] <- PSE: CPU Support 4MB Size Pages Edx [4] <- TSC: Tsc Present (See Rdtsc Command) EDX [5] < - MSR: CPU HAVE K5 Compatible MSRS EDX [6] <- 0 (reserved) EDX [7] <
